RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock X1 clock External main system clock Condition Before Stopping Clock (Invalidating External Clock Input) CPU and peripheral hardware clocks operate with a clock other than the high-speed system clock. (CLS = 0 and MCS = 0, or CLS = 1) XT1 clock CPU and peripheral hardware clocks operate with a clock other than the subsystem clock. (CLS = 0) High-speed on-chip oscillator clock CPU and peripheral hardware clocks operate with a clock other than the high-speed on-chip oscillator clock. (CLS = 0 and MCS = 1, or CLS = 1) Setting of CSC Register Flags MSTOP = 1 XTSTOP = 1 HIOSTOP = 1 (4) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case, If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC)) = 1 clear the OSTC register to 00H. Remark The oscillation stabilization time counter starts counting in the following cases. When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 MSTOP = 0) When the STOP mode is released R01UH0317EJ0004 Rev. 0.04 277 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC MOST 8 MOST 9 MOST 10 MOST 11 MOST 13 MOST 15 R01UH0317EJ0004 Rev. 0.04 278 Feb. 22, 2013 MOST 17 MOST 18 MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status 8 9 10 11 13 15 17 18 fX = 10 MHz fX = 20 MHz 0 0 0 0 0 0 0 0 2 8 /fX max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 8 /fX min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 9 /fX min. 51.2 s min. 25.6 s min. 1 1 1 0 0 0 0 0 2 10 /fX min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 11 /fX min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 13 /fX min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 15 /fX min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 17 /fX min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 18 /fX min. 26.21 ms min. 13.11 ms min. Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register. If the X1 clock starts oscillation while the high-speed on-chip oscillator clock or subsystem clock is being used as the CPU clock. If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts (“a” below). X1 pin voltage waveform Remark fX: X1 clock oscillation frequency STOP mode release a
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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