RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit Serial array unit includes the following hardware. Table 12-1. Configuration of Serial Array Unit Item Configuration Shift register 16 bits Buffer register Serial data register mn (SDRmn) Note Serial clock I/O SCK00, SCK01, SCK10 pins (for 3-wire serial I/O), SCL11 pins (for simplified I 2 C) Serial data input SI00, SI01, SI10 pins (for 3-wire serial I/O) Serial data output SO00, SO01, SO10, pins (for 3-wire serial I/O) Serial data I/O SDA11 pins (for simplified I 2 C) Control registers Peripheral enable register 0 (PER0) Serial clock select register m (SPSm) Serial channel enable status register m (SEm) Serial channel start register m (SSm) Serial channel stop register m (STm) Serial output enable register m (SOEm) Serial output register m (SOm) Serial output level register m (SOLm) Note During operation (SEmn = 1) Serial data register mn (SDRmn) Serial mode register mn (SMRmn) Serial communication operation setting register mn (SCRmn) Serial status register mn (SSRmn) Serial flag clear trigger register mn (SIRmn) Serial communication pin select register (STSEL) Port input mode registers 0, 1, 3, 5 to 7, 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13) Port output mode register (POM) Port mode registers 0, 1, 3, 5 to 7 (PM0, PM1, PM3, PM5 to PM7) Port registers 0, 1, 3, 5 to 7 (P0, P1, P3, P5 to P7) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10), r: IIC number (r = 11) R01UH0317EJ0004 Rev. 0.04 559 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT INTTM23 Peripheral enable register 0 (PER0) PRS SAU0EN 013 fCLK Serial clock I/O pin (SCK00) Serial data input pin (SI00) Serial clock I/O pin (SCK01) Serial data input pin (SI01) Channel 0 Note 2 Note 2 TXE 00 RXE 00 Channel 1 Selector PRS 012 Figure 12-1. Block Diagram of Serial Array Unit 0 Serial clock select register 0 (SPS0) 4 Edge detection PRS 011 Selector Serial pin selection (see Figure 12-2) DAP 00 Edge/level detection PRS 010 PRS 003 fCLK/2 0 - fCLK/2 11 CK01 CK00 CKP 00 0 Prescaler PRS 002 4 Selector PRS 001 PRS 000 fCLK/2 0 - fCLK/2 11 CKS 00 CCS 002 STS 000 Serial mode register 00 (SMR00) DIR 0 0 0 0 00 Communication controller Serial transfer end interrupt (INTCSI01) R01UH0317EJ0004 Rev. 0.04 560 Feb. 22, 2013 Note 1 Serial communication operation setting register 00 (SCR00) CK01 CK00 Edge/level detection Serial output register 0 (SO0) 0 0 0 0 0 0 CKO01 CKO00 0 0 0 0 0 0 SO01 SO00 fSCK Selector fMCK Selector Serial data register 00 (SDR00) Clock controller fTCLK DLS 002 Shift register DLS 001 DLS 000 CSI00 CSI01 TSF 00 Communication status BFF 00 Communication controller 0 0 SE01 SE00 0 0 SS01 SS00 0 0 ST01 ST00 0 0 SOE01 SOE00 0 0 SOL01 SOL00 FECT 00 Interrupt controller Serial flag clear trigger register 00 (SIR00) FEF 00 Serial pin selection (see Figure 12-2) Output controller PECT 00 Error controller PEF 00 OVCT 00 OVF 00 Serial status register 00 (SSR00) Clear Error information Serial channel enable status register 0 (SE0) Serial channel start register 0 (SS0) Serial channel stop register 0 (ST0) Serial output enable register 0 (SOE0) Serial output level register 0 (SOL0) Serial data output pin (SO00) Serial transfer end interrupt (INTCSI00) Serial data output pin (SO01) Notes 1. When operation is stopped (SEmn = 0), the higher 7 bits become the clock division setting section and the lower bits are fixed to 0. During operation (SEmn = 1), it becomes a buffer register. 2. Serial pin selection (see Figure 12-2)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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RL78/D1A User’s Manual: Hardware
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