RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 22 RESET FUNCTION
Table 22-2. Hardware Statuses After Reset Acknowledgment (1/7)
Hardware After Reset
Note 1
Acknowledgment
Program counter (PC) The contents of the
reset vector table
(0000H, 0001H) are
set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
RAM
Data memory
Note 2
Undefined
General-purpose registers
Note 2
Undefined
Port registers (P0 to P9, P13 to P15) (output latches) 00H
Port mode registers 0 to 9, 13 to 15 (PM0 to PM9, PM13 to PM15) FFH Note3
Port input mode registers 0, 1, 3, 5 to 7, 13 (PIM0, PIM1, PIM3, PIM5 to PIM7, PIM13) 00H
Port output mode registers (POM) 00H
Pull-up resistor option registers 0, 1, 3 to 9, 13, 14 (PU0, PU1, PU3 to PU9, PU13, PU14) 00H (PU4 is 01H)
Clock operation mode control register (CMC) 00H
Clock operation status control register (CSC) C0H
System clock control register (CKC) 00H
Oscillation stabilization time counter status register (OSTC) 00H
Oscillation stabilization time select register (OSTS) 07H
Peripheral enable registers 0, 1 (PER0, PER1) 00H
High-speed on-chip oscillator frequency select register (HOCODIV) Undefined
High-speed on-chip oscillator trimming register (HIOTRM) Undefined
PLL control register (PLLCTL) 00H
PLL status register (PLLSTS) 00H
Peripheral clock select register (PCKSEL) 00H
FMP clock division selection register (MDIV) 00H
Timer input select registers 00, 01, 10, 11, 20, 21 (TIS00, TIS01, TIS10, TIS11, TIS20, TIS21) 00H
Timer array unit Timer data registers 00 to 07, 10 to 17, 20 to 27
(TDR00 to TDR07, TDR10 to TDR17, TDR20 to TDR27)
0000H
Timer mode registers 00 to 07, 10 to 17, 20 to 27
(TMR00 to TMR07, TMR10 to TMR17, TMR20 to TMR27)
0000H
Timer status registers 00 to 07 (TSR00 to TSR07) 0000H
Timer counter registers 00 to 07, 10 to 17, 20 to 27 (TCR00 to TCR07, TCR10 to TCR17,
TCR20 to TCR27)
FFFFH
Timer channel enable status register 0 (TE0) 0000H
Timer channel start register 0 (TS0) 0000H
Timer channel stop register 0 (TT0) 0000H
Timer clock select register 0 to 2(TPS0 to TPS2) 0000H
Timer output register 0 (TO0) 0000H
Timer output enable register 0 (TOE0) 0000H
Timer output level register 0 (TOL0) 0000H
Timer output mode registers 0 to 2 (TOM0 to TOM2) 0000H
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.
3. Value afte reset is FEH only for PM3.
Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
R01UH0317EJ0004 Rev. 0.04 1097
Feb. 22, 2013