RL78/D1A User's Manual: Hardware - Renesas

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Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
9.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCL pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
9.4.1 Operation as output pin
The PCL pin is output as the following procedure.
Select the PCL output pin by the PCLSEL bit in the SGSEL register.
Select the output frequency with bits 0 to 3 (CCS00 to CCS02, CSEL0) of the clock output select register 0
(CKS0) of the PCL pin (output in disabled status).
Set bit 7 (PCLOE0) of the CKS0 register to 1 to enable clock/buzzer output.
Remarks The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOE0 bit) is switched. At this time, pulses with a narrow width are not output.
Figure 9-6 shows enabling or stopping output using the PCLOE0 bit and the timing of outputting the clock.
Figure 9-6. Remote Control Output Application Example
9.5 Cautions of clock output/buzzer output controller
When the main system clock is selected for the PCL output, if STOP or HALT mode is entered within 1.5 main system
clock cycles after the output is disabled (PCLOE0 = 0), the PCL output width becomes shorter.
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Feb. 22, 2013