RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 22 RESET FUNCTION
Table 22-2. Hardware Statuses After Reset Acknowledgment (3/7)
Hardware Status After Reset
Note 1
Acknowledgment
Serial array unit (SAU) Serial data registers 00, 01, 10, 11 (SDR00, SDR01, SDR10, SDR11) 0000H
Serial status registers 00, 01, 10, 11 (SSR00, SSR01, SSR10, SSR11) 0000H
Serial flag clear trigger registers 00, 01, 10, 11 (SIR00, SIR01, SIR10, SIR11) 0000H
Serial mode registers 00, 01, 10, 11 (SMR00, SMR01, SMR10, SMR11) 0020H
Serial communication operation setting registers 00, 01, 10, 11 (SCR00, SCR01,
SCR10, SCR11)
0087H
Serial channel enable status registers 0, 1 (SE0, SE1) 0000H
Serial channel start registers 0, 1 (SS0, SS1) 0000H
Serial channel stop registers 0, 1 (ST0, ST1) 0000H
Serial clock select registers 0, 1 (SPS0, SPS1) 0000H
Serial output registers 0, 1 (SO0, SO1) 0303H
Serial output enable registers 0, 1 (SOE0, SOE1) 0000H
Serial output level registers 0, 1 (SOL0, SOL1) 0000H
Serial communication pin select register 0, 1(STSEL0, STSEL1) 00H
DMA controller DMA SFR address registers 0 to 3 (DSA0 to DSA3) 00H
DMA RAM address registers 0 to 3 (DRA0 to DRA3) 00H
DMA byte count registers 0 to 3 (DBC0 to DBC3) 00H
DMA mode control registers 0 to 3 (DMC0 to DMC3) 00H
DMA operation control registers 0 to 3 (DRC0 to DRC3) 00H
Interrupt Request flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L, 3H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H, IF3L, IF3H)
00H
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H, 3L, 3H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H, MK3L, MK3H)
FFH
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 03L, 03H,
10L, 10H, 11L, 11H, 12L, 12H, 13L, 13H (PR00L, PR00H, PR01L, PR01H,
PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L,
PR12H, PR13L, PR13H)
FFH
External interrupt rising edge enable register 0 (EGP0) 00H
External interrupt falling edge enable register 0 (EGN0) 00H
Note 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
Remark The special function register (SFR) mounted depend on the product. See 3.1.4 Special function registers
(SFRs) and 3.1.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
R01UH0317EJ0004 Rev. 0.04 1099
Feb. 22, 2013