RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1307 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 Retry-number 2 +1 where the retry-number is calculated according F05DC C0MASK4L (CAN0 module mask 4 register L) - - E - - - - - - - - to the following method: (Abort under radix point) For read F05DE C0MASK4H (CAN0 module mask 4 register H) - - E - - - - - - - - Min. (1/fCAN) 3/ (1/fCLK) F05E0 C0CTRL (CAN0 module control register) - - E - - - - - - - - Max. (1/fCAN) 4/ (1/fCLK) For 8 bit-write F05E2 C0LEC (CAN0 module last error information registe) - E - - - - - - - - - Min. (1/fCAN) 4/ (1/fCLK) Max. (1/fCAN) 5/ (1/fCLK) F05E3 C0INFO (CAN0 module information register) - R - - - - - - - - - For 16 bit-write F05E4 C0ERC (CAN0 module error counter register) - - R - - - - - - - - Min. (1/fCAN) 2/ (1/fCLK) Max. (1/fCAN) 3/ (1/fCLK) F05E6 C0IE (CAN0 module interrupt enable register) - - E - - - - - - - - F05E8 C0INTS (CAN0 module interrupt status register) - - E - - - - - - - - F05EA C0BRP (CAN0 module bit rate prescaler register) - E - - - - - - - - - F05EC C0BTR (CAN0 module bit rate register) - - E - - - - - - - - F05EE C0LIPT (CAN0 module last in-pointer register) - R - - - - - - - - - F05F0 C0RGPT (CAN0 module receive history list register) - - E - - - - - - - - F05F2 C0LOPT (CAN0 module last out-pointer register) - R - - - - - - - - - F05F4 C0TGPT (CAN0 module transmit history list register) - - E - - - - - - - - F05F6 C0TS (CAN0 module time stamp register) - - E - - - - - - - - F0600 C0MDB0100 (CAN0 message data byte 01 register 00) - - E - - - - - - - - C0MDB000 - E - - - - - - - - - F0601 C0MDB100 - E - - - - - - - - - F0602 C0MDB2300 (CAN0 message data byte 23 register 00) - - E - - - - - - - - C0MDB200 - E - - - - - - - - - F0603 C0MDB300 - E - - - - - - - - - F0604 C0MDB4500 (CAN0 message data Byte 45 register 00) - - E - - - - - - - - C0MDB400 - E - - - - - - - - - F0605 C0MDB500 - E - - - - - - - - - F0606 C0MDB6700 (CAN0 message data byte 67 register 00) - - E - - - - - - - - C0MDB600 - E - - - - - - - - - F0607 C0MDB700 - E - - - - - - - - - F0608 C0MDLC00 (CAN0 message data length register 00) - E - - - - - - - - - 1307 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1308 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 Retry-number 2 +1 where the retry-number is calculated according F0609 C0MCONF00 (CAN0 message configuration register 00) - E - - - - - - - - - to the following method: (Abort under radix point) For read F060A C0MIDL00 (CAN0 message ID register 00L) - - E - - - - - - - - Min. (1/fCAN) 3/ (1/fCLK) Max. (1/fCAN) 4/ (1/fCLK) F060C C0MIDH00 (CAN0 message ID register 00H) - - E - - - - - - - - For 8 bit-write Min. (1/fCAN) 4/ (1/fCLK) F060E C0MCTRL00 (CAN0 message control register 00) - - E - - - - - - - - Max. (1/fCAN) 5/ (1/fCLK) C0MDB0101 (CAN0 message data byte 01 register 01) - - E - - - - - - - - For 16 bit-write Min. (1/fCAN) 2/ (1/fCLK) F0610 C0MDB001 - E - - - - - - - - - Max. (1/fCAN) 3/ (1/fCLK) F0611 C0MDB101 - E - - - - - - - - - F0612 C0MDB2301 (CAN0 message data byte 23 register 01) - - E - - - - - - - - C0MDB201 - E - - - - - - - - - F0613 C0MDB301 - E - - - - - - - - - F0614 C0MDB4501 (CAN0 message data byte 45 register 01) - - E - - - - - - - - C0MDB401 - E - - - - - - - - - F0615 C0MDB501 - E - - - - - - - - - F0616 C0MDB6701 (CAN0 message data byte 67 register 01) - - E - - - - - - - - C0MDB601 - E - - - - - - - - - F0617 C0MDB701 - E - - - - - - - - - F0618 C0MDLC01 (CAN0 message data length register 01) - E - - - - - - - - - F0619 C0MCONF01 (CAN0 message configuration register 01) - E - - - - - - - - - F061A C0MIDL01 (CAN0 message ID register 01L) - - E - - - - - - - - F061C C0MIDH01 (CAN0 message ID register 01H) - - E - - - - - - - - F061E C0MCTRL01 (CAN0 message control register 01) - - E - - - - - - - - F0620 C0MDB0102 (CAN0 message data byte 01 register 02) - - E - - - - - - - - C0MDB002 - E - - - - - - - - - F0621 C0MDB102 - E - - - - - - - - - F0622 C0MDB2302 (CAN0 message data byte 23 register 02) - - E - - - - - - - - C0MDB202 - E - - - - - - - - - F0623 C0MDB302 - E - - - - - - - - - F0624 C0MDB4502 (CAN0 message data byte 45 register 02) - - E - - - - - - - - 1308 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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RL78/D1A User's Manual: Hardware - Renesas

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