RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 19 DMA CONTROLLER
Figure 19-4. Format of DMA Mode Control Register n (DMCn) (2/3)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
(When n = 0 or 1)
IFCn IFCn IFCn
3 2 1
IFCn
0
Selection of DMA start source Note
Trigger signal Trigger contents
0 0 0 0 Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0 0 0 1 INTTM00 End of timer channel 0 count or capture
end interrupt
0 0 1 0 INTTM01 End of timer channel 1 count or capture
end interrupt
0 0 1 1 INTTM03 End of timer channel 3 count or capture
end interrupt
0 1 0 0 INTTM05 End of timer channel 5 count or capture
end interrupt
0 1 0 1 INTTM07 End of timer channel 7 count or capture
end interrupt
0 1 1 0 INTTM10 End of timer channel 10 count or capture
end interrupt
0 1 1 1 INTTM11 End of timer channel 11 count or capture
end interrupt
1 0 0 0 INTTM12 End of timer channel 12 count or capture
end interrupt
1 0 0 1 INTIIC11 IIC11 end of transfer interrupt
1 0 1 0 INTLT0 LIN UART0 (UARTF0) transmission
interrupt
1 0 1 1 INTLR0 LIN UART0 (UARTF0) reception interrupt
1 1 0 0 INTCSI00 CSI00 end of transfer interrupt
1 1 0 1 INTCSI01 CSI01 end of transfer interrupt
1 1 1 0 INTAD A/D conversion end interrupt
1 1 1 1 Setting prohibited
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 0, 1)
R01UH0317EJ0004 Rev. 0.04 1032
Feb. 22, 2013