RL78/D1A User's Manual: Hardware - Renesas

R01UH0317EJ0004 Rev. 0.04 1282
Feb. 22, 2013
Necessary WAIT I/O register(SFR) name R/W Bit R/W
Address
READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0
- - - - F0062
- - - - F0064
- - - - F0065
- - - - F0066
- - - - F0068
- - - - F0069
- - - - F006A
TNFCS0 (Noise filter clock select register for each channel of TAU unit0) E E - E E E E E E E E
TNFCS0_7 TNFCS0_6 TNFCS0_5 TNFCS0_4 TNFCS0_3 TNFCS0_2 TNFCS0_1 TNFCS0_0 E E E E E E E E
TNFEN1 (Noise filter enable register for each channel of TAU unit1) E E - E E E E E E E E
TNFEN1_7 TNFEN1_6 TNFEN1_5 TNFEN1_4 TNFEN1_3 TNFEN1_2 TNFEN1_1 TNFEN1_0 E E E E E E E E
TNFSMP1 (Sampling clock select of noise filter for unit1 (2set)) E E - E E E E E E E E
TNFSMP113 TNFSMP112 TNFSMP111 TNFSMP110 TNFSMP103 TNFSMP102 TNFSMP101 TNFSMP100 E E E E E E E E
TNFCS1 (Noise filter clock select register for each channel of TAU unit1) E E - E E E E E E E E
TNFCS1_7 TNFCS1_6 TNFCS1_5 TNFCS1_4 TNFCS1_3 TNFCS1_2 TNFCS1_1 TNFCS1_0 E E E E E E E E
TNFEN2 (Noise filter enable register for each channel of TAU unit2) E E - E E E E E E E E
TNFEN2_7 TNFEN2_6 TNFEN2_5 TNFEN2_4 TNFEN2_3 TNFEN2_2 TNFEN2_1 TNFEN2_0 E E E E E E E E
TNFSMP2 (Sampling clock select of noise filter for unit2(2set)) E E - E E E E E E E E
TNFSMP213 TNFSMP212 TNFSMP211 TNFSMP210 TNFSMP203 TNFSMP202 TNFSMP201 TNFSMP200 E E E E E E E E
TNFCS2 (Noise filter clock select register for each channel of TAU unit2) E E - E E E E E E E E
TNFCS2_7 TNFCS2_6 TNFCS2_5 TNFCS2_4 TNFCS2_3 TNFCS2_2 TNFCS2_1 TNFCS2_0 E E E E E E E E
- - - - F006E ADPC (A/D port configuration register) - E - - - - - - - - -
- - - - F006F
- - - - F0070
- - - - F0071
- - - - F0072
- - - - F0073
- - - - F0074
- - - - F0075
POM (Port output mode register) E E - R R E E E E E E
POM_5 POM_4 POM_3 POM_2 POM_1 POM_0 - - E E E E E E
TIS00 (Timer input select register 00) E E - E E R E E E R E
TIS031 TIS030 TIS020 TIS011 TIS010 TIS000 E E - E E E - E
TIS01 (Timer input select register 01) E E - E E R E E E R E
TIS071 TIS070 TIS060 TIS051 TIS050 TIS040 E E - E E E - E
TIS10 (Timer input select register 10) E E - E E R E E E R R
TIS131 TIS130 TIS120 TIS111 TIS110 E E - E E E - -
TIS11 (Timer input select register 11) E E - E E E E E E E E
TIS171 TIS170 TIS161 TIS160 TIS151 TIS150 TIS141 TIS140 E E E E E E E E
TIS20 (Timer input select register 20) E E - E E E E E E E E
TIS231 TIS230 TIS221 TIS220 TIS211 TIS210 TIS201 TIS200 E E E E E E E E
TIS21 (Timer input select register 21) E E - E E E E E E E E
TIS271 TIS270 TIS261 TIS260 TIS251 TIS250 TIS241 TIS240 E E E E E E E E
1282
RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS
Specifications in this document are tentative and subject to change.
Under development Preliminary document