RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (15) LIN-UARTn ID setting register (UFnID) The UFnID register is an 8-bit register that stored a PID that has been received when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and during a LIN communication. See 13.7 LIN Communication Automatic Baud Rate Mode for details. Also, when in normal UART mode (UFnMD1, UFnMD0 = 00B) and expansion bit data comparison is enabled (UFnCL = UFnEBE = UFnEBC = 1), the 8 bits (UFnRX7 to UFnRX0) of the receive data and the UFnID register are compared upon a match between the received expansion bit and the expansion bit detection level (UFnEBL). See 13.8.3 Expansion bit mode reception (with data comparison) for details. Be sure to execute LIN communication by setting the reception enable bit (the UFnRXE bit of the UFnCTL0 register) to 0 when specifying a comparison value, and then setting the bit to 1. This register can be read or written in 8-bit units. Reset input sets this register to 00H. Figure 13-15. Format of LIN-UARTn ID Setting Register (UFnID) Address: F024EH (UF0ID), F026EH (UF1ID) After reset: 00H R/W 7 6 5 4 3 2 1 0 UFnID UFnID7 UFnID6 UFnID5 UFnID4 UFnID3 UFnID2 UFnID1 UFnID0 (n = 0, 1) Caution Set to 00H when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B). R01UH0317EJ0004 Rev. 0.04 709 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (16) LIN-UARTn buffer registers 0 to 8 (UFnBUF0 to UFnBUF8) The UFnBUF0 to UFnBUF8 registers are 8-bit buffer registers. These registers can be used when transmitting data in normal UART mode (UFnMD1 and UFnMD0 = 00B) and when transmitting and receiving data in automatic baud rate mode (UFnMD1 and UFnMD0 = 11B). When in normal UART mode (UFnMD1, UFnMD0 = 00B), data will be sequentially transmitted from the UFnBUF0 register by setting the UFnTRQ bit. When in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and during response transmission (UFnTRQ = 1), the transmit data in UFnBUF0 will be transmitted sequentially, but the received data will not be stored. When in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and during response reception (UFnRRQ = 1), the received data will be stored sequentially, starting from the UFnBUF0 register. See 13.6.1 UART buffer mode transmission and 13.7 LIN Communication Automatic Baud Rate Mode for details. These registers can be read or written in 8-bit units. Reset input sets these registers to 00H. Figure 13-16. Format of LIN-UARTn Buffer Registers 0 to 8 (UFnBUF0 to UFnBUF8) Address: F024FH (UF0BUF0), F0250H (UF0BUF1), After reset: 00H R/W UFnBUFm (n = 0, 1, m = 0 to 8) F0251H (UF0BUF2), F0252H (UF0BUF3), F0253H (UF0BUF4), F0254H (UF0BUF5), F0255H (UF0BUF5), F0256H (UF0BUF7), F0257H (UF0BUF8) F026FH (UF1BUF0), F0270H (UF1BUF1), F0271H (UF1BUF2), F0272H (UF1BUF3), F0273H (UF1BUF4), F0274H (UF1BUF5), F0275H (UF1BUF6), F0276H (UF1BUF7), F0277H (UF1BUF8) 7 6 5 4 3 2 1 0 Caution These registers cannot be used when expansion bits are enabled (UFnEBE = UFnCL = 1). R01UH0317EJ0004 Rev. 0.04 710 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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RL78/D1A User’s Manual: Hardware
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