RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Reset Figure 24-7. Processing Procedure After an Interrupt Is Generated No Yes INTLVI generated Save processing LVISEN = 1 LVILV = 0 LVISEN = 0 LVIOMSK = 0 LVD reset generated No LVISEN = 1 LVIMD = 0 Yes LVISEN = 0 Normal operation Perform required save processing. Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1). Set the LVILV bit to 0 to set the high-voltage detection level (VLVDH). Set the LVISEN bit to 0 to enable voltage detection. The MCU returns to normal operation when internal reset by voltage detector (LVD) is not generated, since a condition of VDD becomes VDD VLVDH. Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) Set the LVIMD bit to 0 to set interrupt mode. Set the LVISEN bit to 0 to enable voltage detection. R01UH0317EJ0004 Rev. 0.04 1129 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 µs or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD. Figure 24-8. shows the procedure for initial setting of interrupt and reset mode. No Figure 24-8. Initial Setting of Interrupt and Reset Mode Power supply started Reset source determined LVIRF = 1 ? Yes LVISEN = 1 Voltage detection stabilization wait time LVIMD = 0 LVISEN = 0 Normal operation Remark fIL: Low-speed on-chip oscillator clock frequency Refer to Figure 24-9. Checking reset source. Check internal reset generation by LVD circuit Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) Count 400 µs or 5 clocks of fIL by software. Set the LVIMD bit to 0 to set interrupt mode. Set the LVISEN bit to 0 to enable voltage detection. R01UH0317EJ0004 Rev. 0.04 1130 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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