RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
(b) Error counter
The error counter counts up when an error has occurred, and counts down upon successful transmission and
reception. The error counter is updated immediately after error detection.
Table 14-14. Error Counter
State Transmission Error Counter
(TEC7 to TEC0)
Receiving node detects an error (except bit error in the active error flag
or overload flag).
Receiving node detects dominant level following error flag of error
frame.
Transmitting node transmits an error flag.
[As exceptions, the error counter does not change in the following
cases.]
ACK error is detected in error passive state and dominant level is
not detected while the passive error flag is being output.
A stuff error is detected in an arbitration field that transmitted a
recessive level as a stuff bit, but a dominant level is detected.
Bit error detection while active error flag or overload flag is being output
(error-active transmitting node)
Bit error detection while active error flag or overload flag is being output
(error-active receiving node)
When the node detects 14 consecutive dominant-level bits from the
beginning of the active error flag or overload flag, and then subsequently
detects 8 consecutive dominant-level bits. When the node detects 8
consecutive dominant levels after a passive error flag
When the transmitting node has completed transmission without error
(±0 if error counter = 0)
Reception Error Counter
(REC6 to REC0)
No change +1 (when REPS bit = 0)
No change +8 (when REPS bit = 0)
+8 No change
+8 No change
No change +8 (when REPS bit = 0)
+8 (during transmission) +8 (during reception,
when REPS bit = 0)
–1 No change
When the receiving node has completed reception without error No change - –1 (1 REC6 to REC0
127, when REPS bit = 0)
- ±0 (REC6 to REC0 = 0,
when REPS bit = 0)
- Value of 119 to 127 is
set (when REPS bit = 1)
(c) Occurrence of bit error in intermission
An overload frame is generated.
Caution If an error occurs, the error flag output (active or passive) is controlled according to the
contents of the transmission error counter and reception error counter before the error
occurred. The value of the error counter is incremented after the error flag has been output.
R01UH0317EJ0004 Rev. 0.04 801
Feb. 22, 2013