RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, high-speed on-chip oscillator clock, or subsystem clock. The operating statuses in the HALT mode are shown below. R01UH0317EJ0004 Rev. 0.04 1077 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION Item HALT Mode Setting Table 21-1. Operating Statuses in HALT Mode (1/3) When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on High-speed on-chip oscillator Clock (fIH) When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEX) System clock Clock supply to the CPU is stopped Main system clock fIH Operation continues (cannot be stopped) Operation disabled fX Operation disabled Operation continues (cannot be stopped) Cannot operate fEX Cannot operate Operation continues (cannot be stopped) Subsystem clock fXT Status before HALT mode was set is retained fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) WUTMMCK0 = 1: Oscillates WUTMMCK0 = 0 and WDTON = 0: Stops WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops PLL Status before HALT mode was set is retained CPU Code flash memory Data flash memory Operation stopped RAM Operation stopped (however, operable when DMA is executed) CREG Status before HALT mode was set is retained Port (latch) Status before HALT mode was set is retained (CPU is stopped, while input/output function is possible by DMA access during HALT mode) Timer array unit Real-time clock (RTC) Interval timer Operable Watchdog timer See CHAPTER 10 WATCHDOG TIMER CLM Operable if fIL is not stopped PCL A/D converter SAU (CSI, IIC) Operable Serial interface LIN-UART (UARTF) CAN controller LCD controller/driver Sound generator Stepper motor controller/driver (with ZPD) Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Voltage detection function External interrupt Internal interrupt Acceptable CRC High-speed CRC Operable operation function General-purpose CRC R01UH0317EJ0004 Rev. 0.04 1078 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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