RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 27 OPTION BYTE
Figure 27-3. Format of Option Byte (000C2H/020C2H)
Address: 000C2H/020C2H Note
7 6 5 4 3 2 1 0
CMODE1 CMODE0 OPTPLL 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
CMODE1 CMODE0 Setting of flash operation mode
1 1 HS (high speed main) mode
Other than above Setting prohibited
OPTPLL PLL hard macro multiplication selection
0 16 selection ( 8 from user view) (If input clock is 4/8 MHz, fPLL = 32 MHz)
1 12 selection ( 6 from user view) (default) (If input clock is 4/8 MHz, FPLL = 24 MHz)
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator
1 0 0 0 32 MHz
0 0 0 0 24 MHz
1 0 0 1 16 MHz
1 0 1 0 8 MHz
1 0 1 1 4 MHz
Other than above Setting prohibited
Note Set the same value as 000C2H to 020C2H when the boot swap operation is used because 000C2H is replaced
by 020C2H.
R01UH0317EJ0004 Rev. 0.04 1157
Feb. 22, 2013