RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER
(3) Duty factor
The minimum pulse width that can be generated is zero (output signal is low) and the maximum pulse width is 255
clock cycles (maximum value of 8-bit compare registers).
The count range of the timer counter defines the duty factor. It can be set by bit MCNTC0.FULL:
count range 01H to FFH (MCNTC0.FULL = 0)
Formula for the duty cycle:
PWM duty = MCMPki / 255 with k = 1 to 4 and i = 0, 1
One count cycle is comprised of 255 clock cycles. A PWM signal with maximum pulse length is a steady high
level signal. The duty factor is 100%.
count range 00H to FFH (MCNTC0.FULL = 1)
Formula for the duty cycle:
PWM duty = MCMPki / 256 with k = 1 to 4 and i = 0, 1
One count cycle is comprised of 256 clock cycles. A PWM signal with maximum pulse length is comprised of 255
clock cycles at high level and one clock cycle at low level. The duty factor is 255/256 *100% = 99.6%.
(4) Operation of 1-bit addition circuit
The precision of the angle of a needle is implicitly defined by the number of bits of the compare registers MCMPk0
and MCMPk1 (8 bit).
If the 1-bit addition circuit is enabled, every second pulse of the PWM signal is extended by one bit (one clock cycle).
In average, a pulse width precision of 1/2 bit (1/2 clock) can be achieved.
The following figures show the timing of PWM output signals with 1-bit addition disabled and enabled.
Remarks 1. The PWM pulse is not generated until the first overflow occurs after the counting operation has been
started.
2. The PWM signal is two cycle counts delayed compared to the overflow signal and the match signal. This
is not depicted in the figures.
(5) Detecting zero points
For the detection of zero points, proceed as follows:
1. Set ZPDn pin to analog input by setting ZPDnEN = 0, select reference level using ZPDnS2 to ZPDnS0, and set
the ZPDkPC bit in the ZPDSi register to 1.
2. Enable ZPD comparator operation by setting ZPDnEN = 1, and wait for comparator stabilization time.
3. Enable ZPDn flag operation by setting TWIN = 1.
4. Apply input signal to ZPDn pin, and start detection operation.
(6) Digital noise filter
The noise removal circuit suppresses short pulses/spikes of the comparator output to gain stable comparison results.
The minimum voltage comparator output pulse width to be validated is configurable by selecting the sampling clock
for the digital noise removal, refer to CMPCTL.DBCL[3:0]. Spikes shorter than 2 sampling cycles are suppressed.
Pulses longer than 3 sampling cycles are recognized as valid pulses. For pulses between 2 and 3 sampling cycles,
the behavior is not defined.
R01UH0317EJ0004 Rev. 0.04 960
Feb. 22, 2013