RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR03H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, PR13H) (R5F10DPJxFB) (3/3) Address: FFFDAH After reset: FFH R/W Symbol 7 6 PR03L TMPR022 TMPR021 TMPR020 TMPR017 TMPR016 TMPR015 TMPR014 C1TRXPR0 Address: FFFDEH After reset: FFH R/W Symbol 7 6 PR13L TMPR122 TMPR121 TMPR120 TMPR117 TMPR116 TMPR115 TMPR114 C1TRXPR1 Address: FFFDBH After reset: FFH R/W Symbol 7 6 5 PR03H 1 1 1 DMAPR03 DMAPR02 TMPR026 TMPR024 TMPR023 Address: FFFDFH After reset: FFH R/W Symbol 7 6 5 PR13H 1 1 1 DMAPR13 DMAPR12 TMPR126 TMPR124 TMPR123 XXPR1X XXPR0X Priority level selection 0 0 Specify level 0 (high priority level) 0 1 Specify level 1 1 0 Specify level 2 1 1 Specify level 3 (low priority level) Caution The above is the bit layout for the R5F10DPJxFB. The available bits differ depending on the product. For details about the bits available for each product, see Table 20-1 and 20-2. Be sure to set bits that are not available to 1. R01UH0317EJ0004 Rev. 0.04 1061 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register 0 (EGP0) These registers specify the valid edge for external interrupt, INTP0 to INTP5, INTPLR0, and INTPLR1. The registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 20-5. Format of External Interrupt Rising Edge Enable Register 0 (EGP0) and External Interrupt Falling Edge Enable Register 0 (EGN0) Address: FFF38H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGP0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FFF39H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGN0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn Valid edge selection of external interrupt 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Table 20-3 shows the ports corresponding to the EGPn and EGNn bits. R01UH0317EJ0004 Rev. 0.04 1062 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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