RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.7 Procedure for processing errors that occurred during simplified I 2 C (IIC11) communication The procedure for processing errors that occurred during simplified I 2 C (IIC11) communication is described in Figures 12-84 and 12-85. Figure 12-84. Processing Procedure in Case of Parity Error or Overrun Error Software Manipulation Hardware Status Remark Reads SDRmn register. BFF = 0, and channel n is enabled to receive data. This is to prevent an overrun error if the next reception is completed during error processing. Reads SSRmn register. Error type is identified and the read value is used to clear error flag. Writes SIRmn register. Error flag is cleared. Only error generated at the point of reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification. Figure 12-85. Processing Procedure in Case of Parity Error (ACK error) in Simplified I 2 C Mode Software Manipulation Hardware Status Remark Reads SDRmn register. BFF = 0, and channel n is enabled to receive data. This is to prevent an overrun error if the next reception is completed during error processing. Reads SSRmn register. Error type is identified and the read value is used to clear error flag. Writes SIRmn register. Error flag is cleared. Only error generated at the point of reading can be cleared, by writing the value read from the SSRmn register to the SIRmn register without modification. Sets STmn bit to 1. SEmn = 0, and channel n stops operation. Creates stop condition. Creates start condition. Sets SSmn bit to 1. SEmn = 1, and channel n is enabled to operate. Remark m: Unit number (m = 1), n: Channel number (n = 1) Slave is not ready for reception because ACK is not returned. Therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. Or, a restart condition is generated and transmission can be redone from address transmission. R01UH0317EJ0004 Rev. 0.04 669 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.8 Relationship Between Register Settings and Pins Tables 12-4 to 12-13 show the relationship between register settings and pins for each channel of serial array units 0, 1. R01UH0317EJ0004 Rev. 0.04 670 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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