RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. • Register configuration during multiplication MDAL (bits 15 to 0) MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] • Register configuration during multiply-accumulation < accumulated value > < accumulated result > MDAL (bits 15 to 0) MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] (The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).) • Register configuration during division [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] = [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] R01UH0317EJ0004 Rev. 0.04 1015 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). (1) Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator. The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 18-5. Format of Multiplication/Division Control Register (MDUC) Address: F00E8H After reset: 00H R/W Symbol 5 4 MDUC DIVMODE MACMODE 0 0 MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM Operation mode selection 0 0 0 Multiplication mode (unsigned) (default) 0 0 1 Multiplication mode (signed) 0 1 0 Multiply-accumulator mode (unsigned) 0 1 1 Multiply-accumulator mode (signed) 1 0 0 Division mode (unsigned), generation or not generation of a division completion interrupt (INTMD) 1 1 0 Division mode (unsigned), not generation of a division completion interrupt (INTMD) Other than above Setting prohibited MACOF Overflow flag of multiply-accumulation result (accumulated value) 0 No overflow 1 With over flow • For the multiply-accumulator mode (unsigned) The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh. • For the multiply-accumulator mode (signed) The bit is set when the result of adding a positive product to a positive accumulated value exceeds 7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated value exceeds 80000000h and is positive. MACSF Sign flag of multiply-accumulation result (accumulated value) 0 The accumulated value is positive. 1 The accumulated value is negative. Multiply-accumulator mode (unsigned): The bit is always 0. Multiply-accumulator mode (signed): The bit indicates the sign bit of the accumulated value. DIVST Note Division operation start/stop 0 Division operation processing complete 1 Starts division operation/division operation processing in progress R01UH0317EJ0004 Rev. 0.04 1016 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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RL78/D1A User’s Manual: Hardware
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