RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-75. Flowchart of Address Field Transmission Starting IIC communication SMRmn, SCRmn: Setting communication SPSm, SDRmn[15:9]: Setting transfer rate Writing 0 to SOmn bit Writing 0 to CKOmn bit Writing 1 to SOEmn bit Writing 1 to SSmn bit Writing address and R/W data to SDRmn Transfer end interrupt generated? Yes Parity error (ACK error) flag PEFmn = 1 ? Address field transmission completed Remark m: Unit number (m = 1), n: Channel number (n = 1) No To data transmission flow and data reception flow Perform initial setting when SEmn = 0. R01UH0317EJ0004 Rev. 0.04 655 Feb. 22, 2013 No Yes ACK reception error
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released. Simplified I 2 C IIC11 Target channel Channel 1 of SAU1 Pins used SCL11, SDA11 Interrupt INTIIC11 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection flag Parity error detection flag (PEF11) Transfer data length 8 bits Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel However, the following condition must be satisfied in each mode of I 2 C. Max. 400 kHz (first mode) Max. 100 kHz (standard mode) Data level Forward output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (for ACK reception timing) Data direction MSB first R01UH0317EJ0004 Rev. 0.04 656 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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RL78/D1A User’s Manual: Hardware
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RL78/D1A User's Manual: Hardware - Renesas

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