RL78/D1A User's Manual: Hardware - Renesas

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R01UH0317EJ0004 Rev. 0.04 1319 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFF2D - - - - FFF2E - - - - FFF2F - - - - FFF30 - - - - FFF31 - - - - FFF32 PM13 (Port mode register 13) E E - R E E E E E E R PM13_6 PM13_5 PM13_4 PM13_3 PM13_2 PM13_1 - E E E E E E - PM14 (Port mode register 14) E E - R R R R R R R E PM14_0 - - - - - - - E PM15 (Port mode register 15) E E - R R R R R R R E PM15_0 - - - - - - - E ADM0 (A/D converter mode register 0) E E - E E E E E E E E ADCS ADMD FR2 FR1 FR0 LV1 LV0 ADCE E E E E E E E E ADS (Analog input channel specification register) E E - R R R R E E E E ADS_3 ADS_2 ADS_1 ADS_0 - - - - E E E E ADM1 (A/D converter mode register 1) E E - E E E R R R E E ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 E E E - - - E E - - - - FFF34 SUBCUDW (Watch error correction register) - - E - - - - - - - - - - - - FFF36 - - - - FFF37 - - - - FFF38 - - - - FFF39 - - - - FFF3C - - - - FFF3D - - - - FFF3E - - - - FFF3F - - - - FFF40 RTCSEL (RTC1Hz pin select register) E E - E E R R E E E E RTCOSEL1 RTCOSEL0 RTCTIS11 RTCTIS10 RTCTIS01 RTCTIS00 E E - - E E E E SMPC (SM port mode control register) E E - E E E E E E E E MOD4 MOD3 MOD2 MOD1 EN4 EN3 EN2 EN1 E E E E E E E E EGP0 (External interrupt rising edge enable register 0) E E - E E E E E E E E EGP0_7 EGP0_6 EGP0_5 EGP0_4 EGP0_3 EGP0_2 EGP0_1 EGP0_0 E E E E E E E E EGN0 (External interrupt falling edge enable register 0) E E - E E E E E E E E EGN0_7 EGN0_6 EGN0_5 EGN0_4 EGN0_3 EGN0_2 EGN0_1 EGN0_0 E E E E E E E E STSEL0 (Serial communication pin select register 0) E E - R E R E E E E E SCSI100 SCSI010 SCSI001 SCSI000 SUARTF1 SUARTF0 - E - E E E E E STSEL1 (Serial communication pin select register 1) E E - E E R R E E E E SIIC1 SIIC0 SCAN1 SCAN0 TMCAN1 TMCAN0 E E - - E E E E TISELSE (Timer input select else register) E E - E E R R R R E E TOTICON1 TOTICON0 TI05SEL1 TI05SEL0 E E - - - - E E SGSEL (Sound generator pin select register) E E - R R R R E E E E PCLSEL SGSEL_2 SGSEL_1 SGSEL_0 - - - - E E E E LCDMD (LCD mode register) E E - R R E E R R R R MDSET1 MDSET0 - - E E - - - - 1319 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
R01UH0317EJ0004 Rev. 0.04 1320 Feb. 22, 2013 Necessary WAIT I/O register(SFR) name R/W Bit R/W Address READ(MIN.) READ(MAX.) WRITE(MIN.) WRITE(MAX.) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 8 16 7 6 5 4 3 2 1 0 - - - - FFF41 - - - - FFF42 - - - - FFF48 - - - - FFF4A - - - - FFF4C - - - - FFF4E LCDM (LCD display mode register) E E - E E R R R E R E LCDON SCOC LCDM_2 LCDM_0 E E - - - E - E LCDC0 (LCD clock control register) E E - R E E E R E E E LCDC0_6 LCDC0_5 LCDC0_4 LCDC0_2 LCDC0_1 LCDC0_0 - E E E - E E E UF0TX (LIN-UART0 transmit data register) - - E - - - - - - - - UF0TXB (LIN-UART0 8-bit transmit data register) - E - - - - - - - - - UF0RX (LIN-UART0 receive data register) - - E - - - - - - - - UF0RXB (LIN-UART0 receive data register) - E - - - - - - - - - UF1TX (LIN-UART1 transmit data register) - - E - - - - - - - - UF1TXB (LIN-UART1 8-bit transmit data register) - E - - - - - - - - - UF1RX (LIN-UART1 receive data register) - - E - - - - - - - - UF1RXB (LIN-UART1 receive data register) - E - - - - - - - - - - - - - FFF50 ITMC (Interval timer control register) - - E - - - - - - - - - - - - FFF52 SEC (Second count register) - E - - - - - - - - - - - - - FFF53 MIN (Minute count register) - E - - - - - - - - - - - - - FFF54 HOUR (Hour count register) - E - - - - - - - - - - - - - FFF55 WEEK (Week count register) - E - - - - - - - - - - - - - FFF56 DAY (Day count register) - E - - - - - - - - - - - - - FFF57 MONTH (Month count register) - E - - - - - - - - - - - - - FFF58 YEAR (Year count register) - E - - - - - - - - - - - - - FFF59 SUBCUD (Watch error correction register) - E - - - - - - - - - - - - - FFF5A ALARMWM (Alarm minute register) - E - - - - - - - - - - - - - FFF5B ALARMWH (Alarm hour register) - E - - - - - - - - - - - - - FFF5C ALARMWW (Alarm day register) - E - - - - - - - - - - - - - FFF5D - - - - FFF5E RTCC0 (Real time counter control register 0) E E - E R E R E E E E RTCE RCLOE1 AMPM CT2 CT1 CT0 E - E - E E E E RTCC1 (Real time counter control register 1) E E - E E R E E R R E WALE WALIE WAFG RIFG RWST RWAIT E E - E E - R E - - - - FFF64 TDR02 (Timer data register 02) - - E - - - - - - - - - - - - FFF66 TDR03 (Timer data register 03) - - E - - - - - - - - - - - - FFF68 TDR04 (Timer data register 04) - - E - - - - - - - - 1320 RL78/D1A APPENDIX A NUMBER OF WAIT CYCLES TO ACCESS I/O REGISTERS Specifications in this document are tentative and subject to change. Under development Preliminary document
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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RL78/D1A User's Manual: Hardware - Renesas

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