RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address. [Operand format] Identifier Description [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable) word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) word[BC] (only the space from F0000H to FFFFFH is specifiable) ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) ES:word[BC] (higher 4-bit addresses are specified by the ES register) OP code byte Figure 3-34. Example of [SP+byte] SP Target memory Memory FFFFFH F0000H R01UH0317EJ0004 Rev. 0.04 139 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of [HL + byte], [DE + byte] OP code byte OP code Low Addr. High Addr. OP code Low Addr. High Addr. rp (HL/DE) Target memory Memory Figure 3-36. Example of word[B], word[C] r (B/C) Target memory Memory Figure 3-37. Example of word[BC] rp (BC) Target memory Memory FFFFFH F0000H FFFFFH F0000H FFFFFH F0000H R01UH0317EJ0004 Rev. 0.04 140 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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33.3.2 High speed on chip oscillato
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RL78/D1A User’s Manual: Hardware
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