RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 15 STEPPER MOTOR CONTROLLER/DRIVER
15.3 Operation
In the following, the operation of the Stepper Motor Controller/Driver module as a driver for external meters is described.
15.3.1 Stepper motor controller/driver operation
This section describes the generation of PWM signals of the driver k for driving external meters. Further, the
explanation about the duty factor, operation of 1-bit addition circuit, detecting zero points and digital noise filter is shown.
Remark k = 1 to 4
(1) Driving meters
External meters can be driven both in full bridge configuration and in half bridge configuration:
Driving meters in full bridge configuration
Deflection of the needle of a meter in full bridge configuration is determined by the sine and cosine value of its
desired angle. Since the PWM signals do not inherit a sign, separate signals for positive and negative sine and
cosine values are generated.
The four signals at pins SMk1 to SMk4 of the driver k are:
– sine side, positive (sin +)
– sine side, negative (sin –)
– cosine side, positive (cos +)
– cosine side, negative (cos –)
Two output control circuits select which signal (sign) for sine side and cosine side is output (bits
MCMPCk.DIR[1:0]). At the remaining two output pins, the signal is set to low level.
To drive meter k in full bridge mode, set bit MCMPCk.AOUT to 0.
Driving meters in half bridge configuration
In this mode, the same signal is sent to both sine pins (SMk1 and SMk2) and both cosine pins (SMk3 and SMk4),
respectively. The setting of output control bits MCMPCk.DIR[1:0] is neglected.
To drive meter k in half bridge mode, set bit MCMPCk.AOUT to 1.
(2) Generation of PWM signals
Bit data corresponding to the length of the PWM pulses has to be written to the compare registers MCMPk0 (sine
side) and MCMPk1 (cosine side).
A timer counter is counting up. The rising edge of the PWM pulse is initiated at the overflow of the counter. The
falling edge of the PWM pulse is initiated when the counter value equals the contents of the compare register.
The absolute pulse length in seconds is defined by the timer count clock (fMC0). Various cycle times can be set via the
timer mode control register MCNTC0.
Instruction
When writing data to compare registers, proceed as follows:
1. Confirm that MCMPCk.TEN = 0.
2. Write 8-bit PWM data to MCMPk0 and MCMPk1.
3. Set MCMPCk.ADB0 and MCMPCk.ADB1 as desired.
4. Set MCMPCk.TEN = 1 to start the counting operation.
The data in MCMPk0/MCMPk1 will automatically be copied to the compare slave register when the counter
overflows. The new pulse width is valid immediately.
Bit MCMPCk.TEN is automatically cleared to 0 by hardware.
R01UH0317EJ0004 Rev. 0.04 959
Feb. 22, 2013