RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS Table 20-2. Flags Corresponding to Interrupt Request Sources Name Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag0 Priority Specification Flag1 Register Bit Register Bit Register Bit Register Bit INTWDTI WDTIIF 0 WDTIMK 0 WDTIPR0 0 WDTIPR1 0 INTLVI LVIIF 1 LVIMK 1 LVIPR0 1 LVIPR1 1 INTP0 PIF0 2 PMK0 2 PPR00 2 PPR10 2 INTP1 INTP2 PIF1 PIF2 IF0L 3 4 PMK1 PMK2 MK0L 3 4 PPR01 PPR02 PR00L 3 4 PPR11 PPR12 PR10L 3 4 INTP3 PIF3 5 PMK3 5 PPR03 5 PPR13 5 INTP4 PIF4 6 PMK4 6 PPR04 6 PPR14 6 INTP5 INTCLM PIF5 CLMIF IF0 7 0 PMK5 CLMMK MK0 7 0 PPR05 CLMPR0 PR00 7 0 PPR15 CLMPR1 PR10 7 0 INTCSI00 CSIIF00 1 CSIMK00 1 CSIPR000 1 CSIPR100 1 INTCSI01 CSIIF01 2 CSIMK01 2 CSIPR001 2 CSIPR101 2 INTDMA0 INTDMA1 DMAIF0 DMAIF1 IF0H 3 4 DMAMK0 DMAMK1 MK0H 3 4 DMAPR00 DMAPR01 PR00H 3 4 DMAPR10 DMAPR11 PR10H 3 4 INTRTC RTCIF 5 RTCMK 5 RTCPR0 5 RTCPR1 5 INTIT ITIF 6 ITMK 6 ITPR0 6 ITPR1 6 INTLT0 LTIF0 7 LTMK0 7 LTPR00 7 LTPR10 7 INTLR0 LRIF0 0 LRMK0 0 LRPR00 0 LRPR10 0 INTLS0 LSIF0 1 LSMK0 1 LSPR00 1 LSPR10 1 INTPLR0 PIFLR0 2 PMKLR0 2 PPR0LR0 2 PPR1LR0 2 INTSG INTTM00 SGIF TMIF00 IF1L 3 4 SGMK TMMK00 MK1L 3 4 SGPR0 TMPR000 PR01L 3 4 SGPR1 TMPR100 PR11L 3 4 INTTM01 TMIF01 5 TMMK01 5 TMPR001 5 TMPR101 5 INTTM02 TMIF02 6 TMMK02 6 TMPR002 6 TMPR102 6 INTTM03 INTAD TMIF03 ADIF IF1 7 0 TMMK03 ADMK MK1 7 0 TMPR003 ADPR0 PR01 7 0 TMPR103 ADPR1 PR11 7 0 INTLT1 LTIF1 1 LTMK1 1 LTPR01 1 LTPR11 1 INTLR1 LRIF1 2 LRMK1 2 LRPR01 2 LRPR11 2 INTLS1 INTPLR1 LSIF1 PIFLR1 IF1H 3 4 LSMK1 PMKLR1 MK1H 3 4 LSPR01 PPR0LR1 PR01H 3 4 LSPR11 PPR1LR1 PR11H 3 4 INTCSI10 CSIIF10 5 CSIMK10 5 CSIPR010 5 CSIPR110 5 INTIIC11 IICIF11 6 IICMK11 6 IICPR011 6 IICPR111 6 INTTM04 TMIF04 7 TMMK04 7 TMPR004 7 TMPR104 7 INTTM05 TMIF05 0 TMMK05 0 TMPR005 0 TMPR105 0 INTTM06 TMIF06 1 TMMK06 1 TMPR006 1 TMPR106 1 INTTM07 TMIF07 2 TMMK07 2 TMPR007 2 TMPR107 2 INTC1ERR C1ERRIF INTC1WUP C1WUPIF IF2L 3 4 C1ERRMK C1WUPMK MK2L 3 4 C1ERRPR0 C1WUPPR0 PR02L 3 4 C1ERRPR1 C1WUPPR1 PR12L 3 4 INTC0ERR C0ERRIF 5 C0ERRMK 5 C0ERRPR0 5 C0ERRPR1 5 INTC0WUP C0WUPIF 6 C0WUPMK 6 C0WUPPR0 6 C0WUPPR1 6 INTC0REC INTC0TRX C0RECIF C0TRXIF IF2 7 0 C0RECMK C0TRXMK MK2 7 0 C0RECPR0 C0TRXPR0 PR02 7 0 C0RECPR1 C0TRXPR1 PR12 7 0 INTTM10 TMIF10 1 TMMK10 1 TMPR010 1 TMPR110 1 INTTM11 TMIF11 2 TMMK11 2 TMPR011 2 TMPR111 2 INTTM12 INTTM13 TMIF12 TMIF13 IF2H 3 4 TMMK12 TMMK13 MK2H 3 4 TMPR012 TMPR013 PR02H 3 4 TMPR112 TMPR113 PR12H 3 4 INTMD MDIF 5 MDMK 5 MDPR0 5 MDPR1 5 INTC1REC C1RECIF 6 C1RECMK 6 C1RECPR0 6 C1RECPR1 6 INTFL FLIF 7 FLMK 7 FLPR0 7 FLPR1 7 INTC1TRX C1TRXIF 0 C1TRXMK 0 C1TRXPR0 0 C1TRXPR1 0 INTTM14 TMIF14 1 TMMK14 1 TMPR014 1 TMPR114 1 INTTM15 TMIF15 2 TMMK15 2 TMPR015 2 TMPR115 2 INTTM16 INTTM17 TMIF16 TMIF17 IF3L 3 4 TMMK16 TMMK17 MK3L 3 4 TMPR016 TMPR017 PR03L 3 4 TMPR116 TMPR117 PR13L 3 4 INTTM20 TMIF20 5 TMMK20 5 TMPR020 5 TMPR120 5 INTTM21 TMIF21 6 TMMK21 6 TMPR021 6 TMPR121 6 INTTM22 INTTM23 TMIF22 TMIF23 IF3 7 0 TMMK22 TMMK23 MK3 7 0 TMPR022 TMPR023 PR03 7 0 TMPR122 TMPR123 PR13 7 0 INTTM24 TMIF24 1 TMMK24 1 TMPR024 1 TMPR124 1 INTTM26 TMIF26 2 TMMK26 2 TMPR026 2 TMPR126 2 INTDMA2 INTDMA3 DMAIF2 DMAIF3 IF3H 3 4 DMAMK2 DMAMK3 MK3H 3 4 DMAPR02 DMAPR03 PR03H 3 4 DMAPR12 DMAPR13 PR13H 3 4 - 0 5 1 5 1 5 1 5 - 0 6 1 6 1 6 1 6 - 0 7 1 7 1 7 1 7 R01UH0317EJ0004 Rev. 0.04 1055 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, and IF3H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, the IF2L and IF2H registers, and the IF3L and IF3H registers are combined to form 16-bit registers IF0, IF1, IF2, and IF3, they can be set by a 16-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) (R5F10DPJxFB) (1/2) Address: FFFE0H After reset: 00H R/W Symbol IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF Address: FFFE1H After reset: 00H R/W Symbol IF0H LTIF0 ITIF RTCIF DMAIF1 DMAIF0 CSIIF01 CSIIF00 CLMIF Address: FFFE2H After reset: 00H R/W Symbol IF1L TMIF03 TMIF02 TMIF01 TMIF00 SGIF PIFLR0 LSIF0 LRIF0 Address: FFFE3H After reset: 00H R/W Symbol IF1H TMIF04 IICIF11 CSIIF10 PIFLR1 LSIF1 LRIF1 LTIF1 ADIF Address: FFFD0H After reset: 00H R/W Symbol IF2L C0RECIF C0WUPIF C0ERRIF C1WUPIF C1ERRIF TMIF07 TMIF06 TMIF05 R01UH0317EJ0004 Rev. 0.04 1056 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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