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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 11 A/D CONVERTER<br />

Table 11-3. A/D Conversion Time Selection (3/4)<br />

(3) When there is stabilization wait time<br />

Normal mode 1, 2 (hardware trigger wait mode)<br />

A/D Converter Mode Mode Conversion Number of Number of Stabilization Stabilization Wait + Conversion Time Selection<br />

Register 0 (ADM0) Clock (fAD) Stabilization Conversion Wait<br />

2.7 V VDD 5.5 V<br />

FR2 FR1 FR0 LV1 LV0<br />

Wait Cock Clock +Conversion fCLK = fCLK = fCLK = fCLK = fCLK =<br />

Time<br />

1 MHz 4 MHz 8 MHz 16 MHz 32 MHz<br />

0 0 0 0 0 Normal fCLK/64 8 fAD 19 fAD 1728/fCLK Setting Setting Setting Setting 54 s<br />

1<br />

(number of<br />

prohibited prohibited prohibited prohibited<br />

0 0 1 fCLK/32 sampling 864/fCLK<br />

54 s 27 s<br />

0 1 0 fCLK/16 clock: 432/fCLK<br />

54 s 27 s 13.5 s<br />

0 1 1 fCLK/8<br />

7 fAD)<br />

216/fCLK 54 s 27 s 13.5 s 6.75 s<br />

1 0 0 fCLK/6 162/fCLK 40.5 s 20.25 s 10.125 s 5.0625 s<br />

1 0 1 fCLK/5 135/fCLK 33.75 s 16.875 s 8.4375 s 4.2188 s<br />

1 1 0 fCLK/4 108/fCLK<br />

R01UH0317EJ0004 Rev. 0.04 516<br />

Feb. 22, 2013<br />

Note<br />

27 s 13.5 s 6.75 s 3.375 s<br />

1 1 1<br />

fCLK/2<br />

54/fCLK 54 s 13.5 s 6.75 s 3.375 s Setting<br />

Note<br />

prohibited<br />

0 0 0 0 1 Normal fCLK/64 8 fAD 17 fAD 1600/fCLK Setting Setting Setting Setting 50 s<br />

2<br />

(number of<br />

prohibited prohibited prohibited prohibited<br />

0 0 1 fCLK/32 sampling 800/fCLK<br />

50 s 25 s<br />

0 1 0 fCLK/16 clock: 400/fCLK<br />

50 s 25 s 12.5 s<br />

0 1 1 fCLK/8<br />

5 fAD)<br />

200/fCLK 50 s 25 s 12.5 s 6.25 s<br />

1 0 0 fCLK/6 150/fCLK 37.5 s 18.75 s 9.375 s 4.6875 s<br />

1 0 1 fCLK/5 125/fCLK 31.25 s 15.625 s 7.8125 s 3.90625 s<br />

1 1 0 fCLK/4 100/fCLK<br />

1 1 1<br />

fCLK/2<br />

Note Setting prohibited when VDD < 3.6 V<br />

Note<br />

Note<br />

25 s 12.5 s 6.25 s 3.125 s<br />

50/fCLK 50 s 12.5 s 6.25 s 3.125 s<br />

Note<br />

Note<br />

Setting<br />

prohibited<br />

Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the<br />

conversion stopped/conversion standby status (ADCS = 0).<br />

2. The above conversion time does not include conversion start time. Conversion start time add in the<br />

first conversion. Select conversion time, taking clock frequency errors into consideration.<br />

3. When hardware trigger wait mode, specify the conversion time, including the stabilization wait time<br />

from the hardware trigger detection.<br />

Remark fCLK: CPU/peripheral hardware clock frequency

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