RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
6.7.5 Operation as input signal high-/low-level width measurement
By starting counting at one edge of TImn and capturing the number of counts at another edge, the signal width (highlevel
width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following
expression.
Signal width of TImn input = Period of count clock ((10000H TSRn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operation clock selected with the CKSmn bit of the
TMRmn register, so an error at a maximum of one clock is generated.
TCRmn operates as an up counter in the capture & one-count mode.
When the channel start trigger (TSmn) is set to 1, TEmn is set to 1 and the TImn pin start edge detection wait status is
set.
When the TImn start valid edge (rising edge of TImn when the high-level width is to be measured) is detected, the
counter counts up in synchronization with the count clock. When the valid capture edge (falling edge of TImn when the
high-level width is to be measured) is detected later, the count value is transferred to TDRmn and, at the same time,
INTTMmn is output. If the counter overflows at this time, the OVF bit of the TSRmn register is set to 1. If the counter does
not overflow, the OVF bit is cleared. TCRmn stops at the value “value transferred to TDRmn + 1”, and the TImn pin start
edge detection wait status is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSRmn register is set to 1. However, the OVF bit is configured as an integral flag, and the correct interval value
cannot be measured if an overflow occurs more than once.
Whether the high-level width or low-level width of the TImn pin is to be measured can be selected by using the CISmn1
and CISmn0 bits of the TMRmn register.
Because this function is used to measure the signal width of the TImn pin input, TSmn cannot be set to 1 while TEmn is
1.
CISmn1, CISmn0 of TMRmn = 10B: Low-level width is measured.
CISmn1, CISmn0 of TMRmn = 11B: High-level width is measured.
Remark m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
R01UH0317EJ0004 Rev. 0.04 424
Feb. 22, 2013