RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 17 SOUND GENERATOR
(2) Tone frequency calculation
The tone frequency can be calculated as:
ftone = fSG0CLK / (([SG0FL buffer] + 1) ([SG0FH buffer] + 1) 2)
where:
fSG0CLK : Frequency of Sound Generator’s input clock
fSG0CLK = fCLK / 2
[SG0FL buffer] : Contents of the SG0FL buffer
[SG0FH buffer] : Contents of the SG0FH buffer
Example
If:
– fCLK = 20 MHz
– fSG0CLK = fCLK / 2 = 10 MHz
– [SG0FL buffer] = 255 (00FFH) (this yields a PWM frequency of 39.01 kHz)
– [SG0FH buffer] = 32 (0020H)
then:
– ftone = 592 Hz
Remark Note that the buffer contents can differ from the contents of the associated register until the next compare
match.
17.3.2 Generating the volume information
The sound volume information is generated by comparing the SG0FL counter value with the contents of the SG0PWM
volume buffer. An RS flipflop is set when the counter matches the SG0FL buffer and reset when the counter reaches the
value of the volume buffer SG0PWM.
SG0FL
counter
value
PWM
signal
(RS flipflop
output)
Figure 17-6. PWM Signal Generation
SG0FL buffer value
(when reached, sets the FF)
SG0PWM buffer value
(when reached, resets the FF)
The duty cycle of the PWM signal is determined by the difference between the contents of the SG0FL counter buffer
and the contents of the SG0PWM volume buffer. The larger the difference, the smaller the duty cycle.
The PWM signal is continually high when the value of the volume buffer is higher than the value of the frequency
compare buffer.
Remark To achieve 100 % duty cycle for all PWM frequencies, SG0FL must not be set to a value above 1FEH.
The PWM signal is continually low when the value of the volume buffer is zero—the sound has stopped.
R01UH0317EJ0004 Rev. 0.04 1007
Feb. 22, 2013
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