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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET)<br />

LCD division<br />

Note 1<br />

resistance<br />

TA = -40 to +85 C, 2.7 V EVDD0 = EVDD1 VDD 3.2 V, VSS = EVSS0 = EVSS1 =0 V<br />

Items Symbols Conditions MIN. TYP. MAX. Unit<br />

LCD Segment output<br />

voltage (unloaded)<br />

LCD Common output<br />

voltage (unloaded)<br />

LCD Segment<br />

Output Voltage<br />

(loaded)<br />

LCD Common Output<br />

Voltage (loaded)<br />

LCD split voltage drive<br />

capability<br />

LCD output resistance<br />

Note 3<br />

(COM)<br />

LCD output resistance<br />

Note 3<br />

(SEG)<br />

RLCD 3 K<br />

VODS IO = 1 A VLCDn-0.05<br />

VLCDn<br />

Note 2 VLCDn+0.05 V<br />

VODC IO = 1 A VLCDn-0.05 VLCDn VLCDn+0.05 V<br />

VODSL0<br />

VODSL1<br />

VODSL2<br />

VODSL3<br />

VODCL0<br />

VODCL1<br />

VODCL2<br />

VODCL3<br />

VLC0<br />

VLC1<br />

VLC2<br />

VLC3<br />

IO = 5 A, all segment<br />

pins at same time<br />

IO = 5 A, all segment<br />

pins at same time<br />

IO = 5 A, all segment<br />

pins at same time<br />

IO = 5 A, all segment<br />

pins at same time<br />

IO = 25 A,<br />

single pin<br />

IO = 25 A,<br />

single pin<br />

IO = 25 A,<br />

single pin<br />

IO = 25 A,<br />

single pin<br />

IO = ±530 A<br />

(10 A*53 seg)<br />

IO = ±530 A<br />

(10 A*53 seg)<br />

IO = ±530 A<br />

(10 A*53 seg)<br />

IO = ±530 A<br />

(10 A*53 seg)<br />

VLCD0-0.6 VLCD0 VLCD0+0.6 V<br />

VLCD1-0.6 VLCD1 VLCD1+0.6 V<br />

VLCD2-0.6 VLCD2 VLCD2+0.6 V<br />

VLCD3-0.6 VLCD3 VLCD3+0.6 V<br />

VLCD0-0.2 VLCD0 VLCD0+0.2 V<br />

VLCD1-0.2 VLCD1 VLCD1+0.2 V<br />

VLCD2-0.2 VLCD2 VLCD2+0.2 V<br />

VLCD3-0.2 VLCD3 VLCD3+0.2 V<br />

VLCD0-0.1 VLCD0 VLCD0+0.1 V<br />

VLCD1-0.1 VLCD1 VLCD1+0.1 V<br />

VLCD2-0.1 VLCD2 VLCD2+0.1 V<br />

VLCD3-0.1 VLCD3 VLCD3+0.1 V<br />

RODC 10 K<br />

RODS 10 K<br />

Notes 1. VLCDn (n= 0..3) represents one of the four possible voltage levels at the LCD pins. See table below for<br />

reference.<br />

VLCDn no step-down transforming (2.7 V ≦VDD) step-down transforming (3.2 V ≦ VDD)<br />

VLCD0 VDD 3/5 VDD<br />

VLCD1 2/3 VDD 2/5 VDD<br />

VLCD2 1/3 VDD 1/5 VDD<br />

VLCD3 VSS VSS<br />

2. Only internal connection. The vaule is design specification.<br />

3. RODC is internal equivalent weight resistance from COM pin + COM IOBUF resistance.<br />

RODS is internal equivalent weight resistance from SEG pin +SEG IOBUF resistance.<br />

R01UH0317EJ0004 Rev. 0.04 1238<br />

Feb. 22, 2013

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