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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 6 TIMER ARRAY UNIT<br />

6.4 Channel Output (TOmn Pin) Control<br />

6.4.1 TOmn pin output circuit configuration<br />

Interrupt signal of the master channel<br />

(INTTMmn)<br />

Interrupt signal of the slave channel<br />

(INTTMmp) Controller<br />

The following describes the TOmn pin output circuit.<br />

Figure 6-40. Output Circuit Configuration<br />

<br />

<br />

TOLmn<br />

TOMmn<br />

TOEmn<br />

R01UH0317EJ0004 Rev. 0.04 391<br />

Feb. 22, 2013<br />

<br />

TOmn register<br />

Set<br />

Reset/toggle<br />

<br />

TOmn write signal<br />

Internal bus<br />

TOmn pin<br />

When TOMmn = 0 (toggle mode), the set value of the TOLmn register is ignored and only INTTMmp (slave<br />

channel timer interrupt) is transmitted to the TOmn register.<br />

When TOMmn = 1 (combination operation mode), both INTTMmn (master channel timer interrupt) and<br />

INTTMmp (slave channel timer interrupt) are transmitted to the TOmn register.<br />

At this time, the TOLmn register becomes valid and the signals are controlled as follows:<br />

When TOLmn = 0: Forward operation (INTTMmn set, INTTMmp reset)<br />

When TOLmn = 1: Reverse operation (INTTMmn reset, INTTMmp set)<br />

When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp (reset signal)<br />

takes priority, and INTTMmn (set signal) is masked.<br />

Remark m: Unit number (m = 0 to 2), n: Channel number, p: Slave channel number<br />

When TOEmn = 1, INTTMmn (master channel timer interrupt) and INTTMmp (slave channel timer interrupt)<br />

are transmitted to the TOmn register. Writing to the TOmn register (TOmn write signal) becomes invalid.<br />

When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.<br />

To initialize the TOmn pin output level, it is necessary to set TOEmn = 0 and to write a value to TOmn.<br />

When TOEmn = 0, writing to TOmn bit to the target channel (TOmn write signal) becomes valid. When<br />

TOEmn = 0 neither INTTMmn (master channel timer interrupt) nor INTTMmp (slave channel timer interrupt) is<br />

transmitted to TOmn register.<br />

The TOmn register can always be read, and the TOmn pin output level can be checked.<br />

Remark m: Unit number (m = 0 to 2), n: Channel number, p: Slave channel number

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