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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

14.5.3 Register bit configuration<br />

Table 14-17. Bit Configuration of CAN Global Registers (1/2)<br />

Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8<br />

000F05C0H C0GMCTRL(W) 0 0 0 0 0 0 0 Clear GOM<br />

000F05C1H<br />

0 0 0 0 0 0 Set EFSD Set GOM<br />

000F05C0H C0GMCTRL(R) 0 0 0 0 0 0 EFSD GOM<br />

000F05C1H<br />

MBON 0 0 0 0 0 0 0<br />

000F05C6H C0GMABT(W) 0 0 0 0 0 0 0 Clear<br />

ABTTRG<br />

000F05C7H<br />

0 0 0 0 0 0 Set Set<br />

ABTCLR ABTTRG<br />

000F05C6H C0GMABT(R) 0 0 0 0 0 0 ABTCLR ABTTRG<br />

000F05C7H<br />

0 0 0 0 0 0 0 0<br />

000F05C8H C0GMABTD 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0<br />

000F05CEH C0GMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0<br />

Table 14-17. Bit Configuration of CAN Global Registers (2/2)<br />

Address Symbol Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8<br />

000F0340H C1GMCTRL(W) 0 0 0 0 0 0 0 Clear GOM<br />

000F0341H<br />

0 0 0 0 0 0 Set EFSD Set GOM<br />

000F0340H C1GMCTRL(R) 0 0 0 0 0 0 EFSD GOM<br />

000F0341H<br />

MBON 0 0 0 0 0 0 0<br />

000F0346H C1GMABT(W) 0 0 0 0 0 0 0 Clear<br />

ABTTRG<br />

000F0347H<br />

0 0 0 0 0 0 Set Set<br />

ABTCLR ABTTRG<br />

000F0346H C1GMABT(R) 0 0 0 0 0 0 ABTCLR ABTTRG<br />

000F0347H<br />

0 0 0 0 0 0 0 0<br />

000F0348H C1GMABTD 0 0 0 0 ABTD3 ABTD2 ABTD1 ABTD0<br />

000F0342H C1GMCS 0 0 0 0 CCP3 CCP2 CCP1 CCP0<br />

Caution The actual register address is calculated as follows:<br />

Register Address = Global Register Area Offset (CH dependent) + Offset Address as listed in table<br />

above<br />

Remark (R) When read<br />

(W) When write<br />

R01UH0317EJ0004 Rev. 0.04 834<br />

Feb. 22, 2013

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