RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 4 PORT FUNCTIONS Figure 4-56. Format of LCD port function Register (4/4) (100-pin products) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W LCDPF0 LCDPF07 LCDPF06 LCDPF05 LCDPF04 LCDPF03 LCDPF02 LCDPF01 LCDPF00 F0050 00H R/W LCDPF1 LCDPF17 LCDPF16 LCDPF15 LCDPF14 LCDPF13 LCDPF12 LCDPF11 LCDPF10 F0051 00H R/W LCDPF3 LCDPF37 LCDPF36 LCDPF35 LCDPF34 LCDPF33 LCDPF32 LCDPF31 LCDPF30 F0053 00H R/W LCDPF5 LCDPF57 LCDPF56 LCDPF55 LCDPF54 LCDPF53 LCDPF52 LCDPF51 LCDPF50 F0055 00H R/W LCDPF7 0 0 LCDPF75 LCDPF74 LCDPF73 LCDPF72 0 0 F0057 00H R/W LCDPF8 LCDPF87 LCDPF86 LCDPF85 LCDPF84 LCDPF83 LCDPF82 LCDPF81 LCDPF80 F0058 00H R/W LCDPF9 LCDPF97 LCDPF96 LCDPF95 LCDPF94 LCDPF93 LCDPF92 LCDPF91 LCDPF90 F0059 00H R/W LCDPF13 0 LCDPF136 0 0 0 0 0 0 F005D 00H R/W LCDPFmn LCDPFmn register function (m = 0, 1, 3, 5, 7 to 9, 13) 0 Used as port or alternate function other than segment output 1 Used as LCD segment signal output R01UH0317EJ0004 Rev. 0.04 231 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register (ADPC) This register switches the P20/ANI0/AVREFP to P27/ANI7, and P150/ANI8 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-57. Format of A/D port configuration Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W ADPC 0 0 0 0 ADPC3 ADPC2 ADPC1 ADPC0 F006E 00H R/W ADPC3 ADPC2 ADPC1 ADPC0 ANI8/P150 ANI7/P27 Analog input (A)/digital I/O (D) switching 0 0 0 0 A A A A A A A A A ANI6/P26 0 0 0 1 D D D D D D D D D 0 0 1 0 D D D D D D D D A 0 0 1 1 D D D D D D D A A 0 1 0 0 D D D D D D A A A 0 1 0 1 D D D D D A A A A 0 1 1 0 D D D D A A A A A 0 1 1 1 D D D A A A A A A 1 0 0 0 D D A A A A A A A 1 0 0 1 D A A A A A A A A Other than the above Setting prohibited, all the channels ANI8-0 are alalog input on ANI5/P25 all hardware sepecification A(Analog): Digital functions (input/output) are disabled. PMmn setting is invalid. D(Digital): Digital functions (input/output) are enabled. PMmn setting is valid. ANI4/P24 R01UH0317EJ0004 Rev. 0.04 232 Feb. 22, 2013 ANI3/P23 ANI2/P22 ANI1/AVREFM/P21 ANI0/AVREFP/P20
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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