RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/D1A, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-9 to 3-14 show correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for Processing Data Addresses. FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF700H FF6FFH F3000H F2FFFH F1000H F0FFFH F0800H F07FFH F0000H EFFFFH 06000H 05FFFH 00000H Figure 3-9. Correspondence Between Data Memory and Addressing (R5F10CGB) Special function register (SFR) 256 bytes General-purpose register 32 bytes RAM Note 2 KB Mirror 49.75 KB Data flash memory 8 KB Reserved Special function register (2nd SFR) 2 KB Reserved Code flash memory 24 KB SFR addressing Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash function. Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0317EJ0004 Rev. 0.04 87 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF700H FF6FFH F3000H F2FFFH F1000H F0FFFH F0800H F07FFH F0000H EFFFFH 08000H 07FFFH 00000H Figure 3-10. Correspondence Between Data Memory and Addressing (R5F10CGC, R5F10DGC) Special function register (SFR) 256 bytes General-purpose register 32 bytes RAM Note 2 KB Mirror 49.75 KB Data flash memory 8 KB Reserved Special function register (2nd SFR) 2 KB Reserved Code flash memory 32 KB SFR addressing Register addressing Short direct addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Note Use of part of this area is prohibited by libraries, when using the self-programming function and data flash function. Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the used RAM area + 10 bytes. R01UH0317EJ0004 Rev. 0.04 88 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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