RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(9) LIN-UARTn transmit data register (UFnTX)
The UFnTX register is a 16-bit register that is used to set transmit data.
This register can be read or written in 16-bit units. When the UFnTX register is read or written in 8-bit units, it can
be accessed as the UFnTXB register.
When no buffer is used and no data consistency error has been detected (UFnDCE = 0) in a transmission enable
state (UFnTXE = 1), transmission is started by writing transmit data to the UFnTX register.
When UFnEBE = 0, transmit data of a character length specified by the UFnCL bit will be transmitted.
When UFnEBE = UFnCL = 1, transmit data of 9-bit length will be transmitted. See 13.5.1 Data format for the
transmit data format.
The last data written to the UFnTX register before it is loaded to the transmit shift register is to be transmitted.
When UFnITS is “0”, successive transmission can be performed by writing the next transmit data to the UFnTX
register after a transmission interrupt request has been generated. When the next transmit data is written before a
transmission interrupt request is generated, the previously written data will be overwritten and only the subsequent
data will be transmitted.
Reset input sets this register to 0000H.
Figure 13-9. Format of LIN-UARTn Transmit Data Register (UFnTX)
Address: FFF48H, FFF49H (UF0TX), FFF4CH, FFF4DH (UF1TX) After reset: 0000H R/W
15 14 13 12 11 10 9 8
UFnTX 0 0 0 0 0 0 0 UFnTX8
(n = 0, 1) 7 6 5 4 3 2 1 0
UFnTX7 UFnTX6 UFnTX5 UFnTX4 UFnTX3 UFnTX2 UFnTX1 UFnTX0
When the data length is specified as 7 bits (UFnCL = 0):
During LSB-first transmission, bits 6 to 0 of the UFnTX register will be transferred as transmit data.
During MSB-first transmission, bits 7 to 1 of the UFnTX register will be transferred as transmit data.
Cautions 1. If the UFnTX register is written while transmission is disabled (UFnTXE = 0), it will not
operate as a transmission start trigger. Consequently, no transmission will be started, even
if transmission is enabled after having written to the UFnTX register while transmission was
disabled.
2. When the UFnTX register is written in 8-bit units (when the UFnTXB register is written), “0” is
written to the UFnTX8 bit.
3. Writing to the UFnTX register is prohibited when using the UFnBUF0 to UFnBUF8 registers.
Remarks 1. When UFnOPT2.UFnITS is “0”, successive transmission can be performed by writing the next
transmit data before transmission is completed, after a transmission interrupt request signal
(INTLTn) has been generated.
2. The UFnTX8 bit is an expansion bit when expansion bits are enabled (UFnEBE = UFnCL = 1).
R01UH0317EJ0004 Rev. 0.04 703
Feb. 22, 2013