ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.355 VPUSH
Vector Push stores multiple consecutive extension registers to the stack.
Encoding T1 / A1 VFPv2, VFPv3, Advanced SIMD
VPUSH is consecutive 64-bit registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 1 imm8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 1 imm8
single_regs = FALSE; d = UInt(D:Vd); imm32 = ZeroExtend(imm8:’00’, 32);
regs = UInt(imm8) DIV 2; // If UInt(imm8) is odd, see “FSTMX”.
if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
Encoding T2 / A2 VFPv2, VFPv3
VPUSH is consecutive 32-bit registers
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 0 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 0 imm8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 1 1 0 1 0 D 1 0 1 1 0 1 Vd 1 0 1 0 imm8
single_regs = TRUE; d = UInt(Vd:D);
imm32 = ZeroExtend(imm8:’00’, 32); regs = UInt(imm8);
if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
FSTMX Encoding T1/A1 behaves as described by the pseudocode if imm8 is odd.
However, there is no UAL syntax for such encodings and their use is deprecated.
For more information, see FLDMX, FSTMX on page A8-101.
A8-696 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B