05.02.2013 Views

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

IVA mismatch with an address range mask, described as an excluded range IVA breakpoint<br />

Note<br />

Support for address range masks on breakpoints is IMPLEMENTATION DEFINED.<br />

Debug Events<br />

For all types of IVA breakpoint, if the conditions in the DBGBCR are met, <strong>and</strong> the instruction is committed<br />

for execution, the BRP generates a Breakpoint debug event if the required DBGBVR comparison, taking<br />

account of the byte address selection <strong>and</strong> any address range masking, hits for the first unit of the instruction.<br />

Table C3-2 shows the conditions for Breakpoint debug event generation by an instruction that comprises<br />

more than one unit of memory, assuming that the conditions in the DBGBCR are met <strong>and</strong> that the instruction<br />

is committed for execution.<br />

Table C3-2 Breakpoint debug event generation for instructions of more than one unit of memory<br />

DBGBVR comparison result a :<br />

First unit b Any subsequent unit b<br />

IVA breakpoint type<br />

Hit - Any Yes<br />

Effect of instruction length in v6 Debug <strong>and</strong> v6.1 Debug<br />

Breakpoint debug<br />

event generated?<br />

Miss Hit Regular, included range, or excluded range UNPREDICTABLE<br />

Step-off No<br />

Miss Miss Any No<br />

a. Taking account of the byte address selection <strong>and</strong> any address range masking.<br />

b. Of the instruction whose IVA is being compared.<br />

If the conditions in the DBGBCR are met, <strong>and</strong> the instruction is committed for execution, the BRP generates<br />

a Breakpoint debug event if the required DBGBVR comparison, taking account of the byte address<br />

selection, hits for the first unit of the instruction.<br />

In v6 Debug <strong>and</strong> v6.1 Debug, it is IMPLEMENTATION DEFINED whether an IVA comparison on an instruction<br />

memory unit other than the first unit, following a breakpoint miss on the first unit of the instruction, can<br />

cause a Breakpoint debug event.<br />

For Java bytecodes, v6 Debug <strong>and</strong> v6.1 Debug specify that a BRP comparison on an oper<strong>and</strong> does not<br />

generate a Breakpoint debug event. A Breakpoint debug is generated only if the BRP hits on the opcode.<br />

For Java bytecodes the instruction memory unit is a byte, <strong>and</strong> the opcode is always the first byte of the<br />

instruction.<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C3-11

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!