ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The System Level Programmers’ Model
1 Configuration valid. The EJVM does not need to update the configuration
registers.
When the JMCR.JE bit is set to 1, the CV bit also controls entry to Jazelle state, see
Controlling entry to Jazelle state on page B1-79.
CD, bit [0] Configuration Disabled bit. This bit is used by an operating system to disable User mode
access to the JIDR and configuration registers:
0 Configuration enabled. Access to the Jazelle registers, including User mode
accesses, operate normally. For more information, see the register descriptions
in Application level configuration and control of the Jazelle extension on
page A2-75.
1 Configuration disabled in User mode. User mode access to the Jazelle registers
are UNDEFINED, and all User mode accesses to the Jazelle registers cause an
Undefined Instruction exception.
For more information about the use of this bit see Monitoring and controlling User mode
access to the Jazelle extension on page B1-80.
The JOSCR provides a control mechanism that is independent of the subarchitecture of the Jazelle
extension. An operating system can use this mechanism to control access to the Jazelle extension. Normally,
this register is used in conjunction with the JMCR.JE bit, see Jazelle Main Configuration Register (JMCR)
on page A2-77.
The JOSCR.CV and JOSCR.CD bits are both set to 0 on reset. This ensures that, subject to some conditions,
an EJVM can operate under an OS that does not support the Jazelle extension. The main condition required
to ensure an EJVM can operate under an OS that does not support the Jazelle extension it that the operating
system never swaps between two EJVM processes that require different settings of the Jazelle configuration
registers.
Two examples of how this condition can be met in a system are:
if there is only ever one process or thread using the EJVM
if all of the processes or threads that use the EJVM use the same static settings of the configuration
registers.
Accessing the JOSCR
To access the JOSCR you read or write the CP14 registers with set to 7, set to c1, set to
c0, and set to 0. For example:
MRC p14, 7, , c1, c0, 0 ; Read Jazelle OS Control Register
MCR p14, 7, , c1, c0, 0 ; Write Jazelle OS Control Register
Note
For maximum compatibility with any future enhancements to the Jazelle extension, ARM strongly
recommends that a read, modify, write sequence is used to update the JOSCR. Updating the register in this
way preserves the value of any of bits [31:2] that might be used by a future expansion.
B1-78 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B