ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
Instruction Details
VABD. , , Encoding T1 / A1, Q = 1
VABD. , , Encoding T1 / A1, Q = 0
VABDL. , , Encoding T2 / A2
where:
See Standard assembler syntax fields on page A8-7. An ARM VABD or VABDL
instruction must be unconditional.
The data type for the elements of the operands. It must be one of:
S8 encoded as size = 0b00, U = 0
S16 encoded as size = 0b01, U = 0
S32 encoded as size = 0b10, U = 0
U8 encoded as size = 0b00, U = 1
U16 encoded as size = 0b01, U = 1
U32 encoded as size = 0b10, U = 1.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
, , The destination vector and the operand vectors, for a long operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
for e = 0 to elements-1
op1 = Elem[D[n+r],e,esize];
op2 = Elem[D[m+r],e,esize];
absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
if long_destination then
Elem[Q[d>>1],e,2*esize] = absdiff;
else
Elem[D[d+r],e,esize] = absdiff;
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-529