ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Note
Common VFP Subarchitecture Specification
In version 1 of the Common VFP subarchitecture, the meaning of the FPEXC.EX bit
changes when the FPSCR.IXE bit is set to 1. The FPSCR.IXE bit can be checked only
after the FPEXC.EX bit is cleared to 0. If FPSCR.IXE is 0, go to step 2 below. If
FPSCR.IXE is set to 1:
the information collected from the VFP registers and the calculated return address
are ignored
the exception-generating instruction is the instruction that bounced, and the
iteration count is the FPSCR.LEN value, as for the FPEXC.DEX == 1 case.
set the return address to the instruction following the bounced instruction.
2. Packages up the information about the VFP instruction and iteration count into pairs in a form
suitable to pass to the Computation Engine, described in step 3.
At this point the packaged information can be sent as a signal to another exception handler in the application,
where the support code continues. Continuing in the application context makes it possible for the support
code to call trap handlers directly, in the application.
3. Executes in software the instruction iterations described in step 2. All configuration information
except vector length is read from the FPSCR.
In previous support code implementations by ARM, this execution is performed by the VFP
Computation Engine function.
If trapped floating-point exceptions are enabled, the Computation Engine calls trap handlers as
required.
If the exceptional condition is an unallocated instruction, the Computation Engine will call a suitable
error routine.
4. Returns to the appropriate return address.
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