ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

G.2 Application level register support
ARMv6 Differences
The ARMv6 core registers are the same as the ARMv7 core registers. For more information, see ARM core
registers on page A2-11. The following sections give more information about ARMv6 application level
register support:
APSR support
Instruction set state.
G.2.1 APSR support
Application Program Status Register (APSR) support in ARMv6 is identical to ARMv7. Program status is
reported in the 32-bit APSR. The format of the APSR is:
31 30 29 28 27 26 24 23 20 19 16 15 0
N Z C V Q RAZ/
SBZP
Reserved GE[3:0] Reserved
See The Application Program Status Register (APSR) on page A2-14 for the APSR bit definitions.
Earlier versions of this manual do not use the term APSR. They refer to the APSR as the CPSR
with restrictions on reserved fields determined by whether the access to the register was privileged or not.
G.2.2 Instruction set state
Instruction set state support in ARMv6 is in general the same as the support available in ARMv7. The only
differences are that:
ThumbEE state is not supported in ARMv6. It is introduced in ARMv7.
In ARMv6 and ARMv6K, but not in ARMv6T2, when the processor is in a privileged mode you must
take care not to attempt to change the instruction set state by writing nonzero values to CPSR.J and
CPSR.T with an MSR instruction. For more information, see Format of the CPSR and SPSRs on
page AppxG-17.
All ARMv6 implementations support the ARM instruction set. The ARMv6 base architecture and ARMv6K
also support a subset of the Thumb instruction set that can be executed entirely as 16-bit instructions. The
only 32-bit instructions in this subset are restricted-range versions of the BL and BLX (immediate)
instructions. See BL and BLX (immediate) instructions, before ARMv6T2 on page AppxG-4 for a
description of how these instructions can be executed as 16-bit instructions.
The supported ARM and Thumb instructions in the ARMv6 base architecture and ARMv6K are
summarized in Instruction set support on page AppxG-10, and the instruction descriptions in Chapter A8
Instruction Details give details of the architecture variants that support each instruction encoding.
Jazelle state is supported as in ARMv7. For more information, see:
Jazelle direct bytecode execution support on page A2-73, for application level information
Jazelle direct bytecode execution on page B1-74, for system level information.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-3