ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

B3.12.15 c0, Cache Size Selection Register (CSSELR)
Virtual Memory System Architecture (VMSA)
The Cache Size Selection Register, CSSELR, selects the current CCSIDR. An ARMv7 implementation
must include a CCSIDR for every implemented cache that is under the control of the processor. The
CSSELR identifies which CP1CSID register can be accessed, by specifying, for the required cache:
the cache level
the cache type, either:
— instruction cache.
— Data cache. The data cache argument is also used for a unified cache.
The CSSELR is:
a 32-bit read/write register
accessible only in privileged modes
when the Security Extensions are implemented, a Banked register
introduced in ARMv7.
The format of the CSSELR is:
31 4 3
1
UNK/SBZP
Level
Bits [31:4] UNK/SBZP.
Level, bits [3:1]
InD, bit [0]
Cache level of required cache. Permitted values are from 0b000, indicating Level 1 cache,
to 0b110 indicating Level 7 cache.
Instruction not Data bit. Permitted values are:
0 Data or unified cache
1 Instruction cache.
If CSSELR is set to indicate a cache that is not implemented, the result of reading CCSIDR is
UNPREDICTABLE.
Accessing CSSELR
To access CSSELR you read or write the CP15 registers with set to 2, set to c0, set to c0,
and set to 0. For example:
MRC p15,2,,c0,c0,0 ; Read Cache Size Selection Register
MCR p15,2,,c0,c0,0 ; Write Cache Size Selection Register
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. B3-95
InD
0