ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Pseudocode Definition
I.1 Instruction encoding diagrams and pseudocode
Instruction descriptions in this manual contain:
An Encoding section, containing one or more encoding diagrams, each followed by some
encoding-specific pseudocode that translates the fields of the encoding into inputs for the common
pseudocode of the instruction, and picks out any encoding-specific special cases.
An Operation section, containing common pseudocode that applies to all of the encodings being
described. The Operation section pseudocode contains a call to the EncodingSpecificOperations()
function, either at its start or after only a condition check performed by if ConditionPassed() then.
An encoding diagram specifies each bit of the instruction as one of the following:
An obligatory 0 or 1, represented in the diagram as 0 or 1. If this bit does not have this value, the
encoding corresponds to a different instruction.
A should be 0 or 1, represented in the diagram as (0) or (1). If this bit does not have this value, the
instruction is UNPREDICTABLE.
A named single bit or a bit in a named multi-bit field. The cond field in bits [31:28] of many ARM
instructions has some special rules associated with it.
An encoding diagram matches an instruction if all obligatory bits are identical in the encoding diagram and
the instruction, and one of the following is true:
the encoding diagram is not for an ARM instruction
the encoding diagram is for an ARM instruction that does not have a cond field in bits [31:28]
the encoding diagram is for an ARM instruction that has a cond field in bits [31:28], and bits [31:28]
of the instruction are not 0b1111.
The execution model for an instruction is:
1. Find all encoding diagrams that match the instruction. It is possible that no encoding diagrams match.
In that case, abandon this execution model and consult the relevant instruction set chapter instead to
find out how the instruction is to be treated. The bit pattern of such an instruction is usually reserved
and UNDEFINED, though there are some other possibilities. For example, unallocated hint instructions
are documented as being reserved and to be executed as NOPs.
2. If the operation pseudocode for the matching encoding diagrams starts with a condition check,
perform that condition check. If the condition check fails, abandon this execution model and treat the
instruction as a NOP. If there are multiple matching encoding diagrams, either all or none of their
corresponding pieces of common pseudocode start with a condition check.
3. Perform the encoding-specific pseudocode for each of the matching encoding diagrams
independently and in parallel. Each such piece of encoding-specific pseudocode starts with a bitstring
variable for each named bit or multi-bit field in its corresponding encoding diagram, named the same
as the bit or multi-bit field and initialized with the values of the corresponding bit(s) from the bit
pattern of the instruction.
AppxI-2 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B