ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Debug State
C5.9 Leaving Debug state
The processor leaves Debug state when a restart request command is received. A restart request can be one
of the following:
An External Restart request. This is a request from the system for the processor to leave Debug state.
The External Restart request enables multiple processors to be restarted synchronously.
The External Restart request is generated by IMPLEMENTATION DEFINED means. Typically this is by
asserting an External Restart request input to the processor.
A restart request command.
In v7 Debug, the restart request command is made by a debugger writing 1 to the DBGDRCR Restart
request bit, see Debug Run Control Register (DBGDRCR), v7 Debug only on page C10-29
A number of flags in the Debug Status and Control Register (DBGDSCR) must be set correctly before
leaving Debug state, see Debug Status and Control Register (DBGDSCR) on page C10-10. The flags that
must be set are:
the sticky exception flags, DBGDSCR[8:6], must be set to 0b000
the Execute ARM Instruction Enable bit, DBGDSCR.ITRen, must be set to 0
the Latched Instruction Complete flag, DBGDSCR.InstrCompl_l, must be set to 1.
In v7 Debug the sticky exception flags are cleared to 0 by writing 1 to the Clear Sticky Exceptions bit of the
DBGDRCR. This operation can be combined with the restart request command. For more information see
Debug Run Control Register (DBGDRCR), v7 Debug only on page C10-29.
If the processor is signaled to leave Debug state without all of these flags set to the correct values the results
are UNPREDICTABLE.
On receipt of a restart request, the processor performs a sequence of operations to leave Debug state.
If DBGDSCR is read during the restart sequence, DBGDSCR.RESTARTED must read as 0 and
DBGDSCR.HALTED must read as 1. At all other times DBGDSCR.RESTARTED must read as 1.
On completion of the restart sequence, the processor leaves Debug state:
DBGDSCR.HALTED is set to 0.
The processor stops ignoring debug events and starts executing instructions from the address held in
the PC, in the mode and instruction set state indicated by the current value of the CPSR. The
execution state bits of the CPSR are honored, and the IT bits state machine is restarted, with the
current value applying to the first instruction executed.
Unless the DBGDSCR.DBGack bit is set to 1, the processor signals to the system that it is in
Non-debug state. Details of this signalling method, including whether it is implemented, are
IMPLEMENTATION DEFINED.
C5-28 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B