ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Common Memory System Architecture Features
The Cache Type Register holds minimum line length values for:
the instruction caches
the data and unified caches.
These values enable a range of addresses to be invalidated in an efficient manner. For details of the register
see:
c0, Cache Type Register (CTR) on page B3-83 for a VMSA implementation
c0, Cache Type Register (CTR) on page B4-34 for a PMSA implementation.
For details of the CP15 c7 encodings for all cache maintenance operations see:
CP15 c7, Cache and branch predictor maintenance functions on page B3-126 for a VMSA
implementation
CP15 c7, Cache and branch predictor maintenance functions on page B4-68 for a PMSA
implementation.
Cache hierarchy abstraction for set/way-based operations
The set/way-based cache maintenance operations are:
Invalidate data cache or unified cache line by set/way
Clean data cache or unified cache line by set/way
Clean and invalidate data cache or unified cache line by set/way
The CP15 c7 encodings of these operations include a field that must be used to specify the cache level for
the operation:
a clean operation cleans from the level of cache specified through to at least the next level of cache,
moving further from the processor
an invalidate operation invalidates only at the level specified.
In addition to these set/way operations, a cache operation is provided for instruction cache maintenance, to
Invalidate all instruction cache lines to the point of unification.
For details of the CP15 c7 encodings for all cache maintenance operations see:
CP15 c7, Cache and branch predictor maintenance functions on page B3-126 for a VMSA
implementation
CP15 c7, Cache and branch predictor maintenance functions on page B4-68 for a PMSA
implementation.
Example code for cache maintenance operations
This code sequence illustrates a generic mechanism for cleaning the entire data or unified cache to the point
of coherency:
MRC p15, 1, R0, c0, c0, 1 ; Read CLIDR
ANDS R3, R0, #&7000000
MOV R3, R3, LSR #23 ; Cache level value (naturally aligned)
BEQ Finished
MOV R10, #0
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