ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.26 BXJ
Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an
address and instruction set specified by a register as though it were a BX instruction.
Encoding T1 ARMv6T2, ARMv7
BXJ Outside or last in IT block
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 1 0 0 Rm 1 0 (0) 0 (1)(1)(1)(1)(0)(0)(0)(0)(0)(0)(0)(0)
m = UInt(Rm);
if BadReg(m) then UNPREDICTABLE;
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
Encoding A1 ARMv5TEJ, ARMv6*, ARMv7
BXJ
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
cond 0 0 0 1 0 0 1 0 (1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1)(1) 0 0 1 0 Rm
m = UInt(Rm);
if m == 15 then UNPREDICTABLE;
A8-64 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B