ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Assembler syntax
VBIC{.} {,} , Encoded as Q = 1
VBIC{.} {,} , Encoded as Q = 0
where:
Instruction Details
See Standard assembler syntax fields on page A8-7. An ARM VBIC instruction must
be unconditional.
An optional data type. It is ignored by assemblers, and does not affect the encoding.
, , The destination vector and the operand vectors, for a quadword operation.
, , The destination vector and the operand vectors, for a doubleword operation.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDEnabled();
for r = 0 to regs-1
D[d+r] = D[n+r] AND NOT(D[m+r]);
Exceptions
Undefined Instruction.
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. A8-549