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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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A2.10.2 Jazelle direct bytecode execution support<br />

Application Level Programmers’ Model<br />

From <strong>ARM</strong>v5TEJ, the architecture requires every system to include an implementation of the Jazelle<br />

extension. The Jazelle extension provides architectural support for hardware acceleration of bytecode<br />

execution by a Java Virtual Machine (JVM).<br />

In the simplest implementations of the Jazelle extension, the processor does not accelerate the execution of<br />

any bytecodes, <strong>and</strong> the JVM uses software routines to execute all bytecodes. Such an implementation is<br />

called a trivial implementation of the Jazelle extension, <strong>and</strong> has minimal additional cost compared with not<br />

implementing the Jazelle extension at all. An implementation that provides hardware acceleration of<br />

bytecode execution is a non-trivial Jazelle implementation.<br />

These requirements for the Jazelle extension mean a JVM can be written to both:<br />

function correctly on all processors that include a Jazelle extension implementation<br />

automatically take advantage of the accelerated bytecode execution provided by a processor that<br />

includes a non-trivial implementation.<br />

Typically, a non-trivial implementation of the Jazelle extension implements a subset of the bytecodes in<br />

hardware, choosing bytecodes that:<br />

can have simple hardware implementations<br />

account for a large percentage of bytecode execution time.<br />

The required features of a non-trivial implementation are:<br />

provision of the Jazelle state<br />

a new instruction, BXJ, to enter Jazelle state<br />

system support that enables an operating system to regulate the use of the Jazelle extension hardware<br />

system support that enables a JVM to configure the Jazelle extension hardware to its specific needs.<br />

The required features of a trivial implementation are:<br />

Normally, the Jazelle instruction set state is never entered. If an incorrect exception return causes<br />

entry to the Jazelle instruction set state, the next instruction executed is treated as UNDEFINED.<br />

The BXJ instruction behaves as a BX instruction.<br />

Configuration support that maintains the interface to the Jazelle extension is permanently disabled.<br />

For more information about trivial implementations see Trivial implementation of the Jazelle extension on<br />

page B1-81.<br />

A JVM that has been written to take advantage automatically of hardware-accelerated bytecode execution<br />

is known as an Enabled JVM (EJVM).<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. A2-73

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