ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

The CPUID Identification Scheme
B5.1 Introduction to the CPUID scheme
In ARM architecture versions before ARMv7, the architecture version is indicated by the Architecture field
in the Main ID Register, see:
c0, Main ID Register (MIDR) on page B3-81, for a VMSA implementation
c0, Main ID Register (MIDR) on page B4-32, for a PMSA implementation.
From ARMv7, the architecture implements an extended processor identification scheme, using a number of
registers in CP15 c0. ARMv7 requires the use of this scheme, and use of the scheme is indicated by a value
of 0xF in the Architecture field of the Main ID Register.
Note
Some ARMv6 processors implemented the scheme before its formal adoption in the architecture.
The CPUID scheme provides information about the implemented:
processor features
debug features
auxiliary features, in particular IMPLEMENTATION DEFINED features
memory model features
instruction set features.
The following sections give more information about the CPUID registers:
Organization of the CPUID registers
General features of the CPUID registers on page B5-3.
The CPUID registers on page B5-4 gives detailed descriptions of the registers.
This chapter also describes the identification registers for any Advanced SIMD or VFP implementation.
These are registers in the shared register space for the Advanced SIMD and VFP extensions, in CP 10 and
CP 11. Advanced SIMD and VFP feature identification registers on page B5-34 describes these registers.
B5.1.1 Organization of the CPUID registers
Figure B5-1 on page B5-3 shows the CPUID registers and their encodings in CP15. Two of the encodings
shown, with == c2 and == {6,7}, are reserved for future expansion of the CPUID scheme. In
addition, all CP15 c0 encodings with == {c3-c7} and == {0-7} are reserved for future
expansion of the scheme. These reserved encodings must be RAZ.
B5-2 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B