ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Virtual Memory System Architecture (VMSA)
The reset value of the MVBAR is UNKNOWN. The MVBAR must be programmed as part of the boot
sequence.
Monitor_Vector_Base_Address, bits [31:5]
Bits [31:5] of the base address of the exception vectors for exceptions that are handled in
Monitor mode. Bits [4:0] of an exception vector is the exception offset, see Table B1-3 on
page B1-31.
Bits [4:0] Reserved, UNK/SBZP.
For details of how the MVBAR is used to determine the exception addresses see Exception vectors and the
exception base address on page B1-30.
Accessing the MVBAR
To access the MVBAR you read or write the CP15 registers with set to 0, set to c12, set
to c0, and set to 1. For example:
MRC p15,0,,c12,c0,1 ; Read CP15 Monitor Vector Base Address Register
MCR p15,0,,c12,c0,1 ; Write CP15 Monitor Vector Base Address Register
B3.12.42 c12, Interrupt Status Register (ISR)
The Interrupt Status Register, ISR, shows whether an IRQ, FIQ or external abort is pending.
The ISR is:
present only when the Security Extensions are implemented
a 32-bit read-only register
accessible only in privileged modes.
a Common register, meaning it is available in the Secure and Non-secure states.
The format of the ISR is:
31 9 8 7 6 5 0
UNK A I F (0) (0) (0) (0) (0) (0)
Bits [31:9] Reserved, UNK.
A, bit [8] External abort pending flag:
0 no pending external abort
1 an external abort is pending.
I, bit [7] Interrupt pending flag. Indicates whether an IRQ interrupt is pending:
0 no pending IRQ
1 an IRQ interrupt is pending.
B3-150 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B