ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

G.7.2 Organization of CP15 registers for an ARMv6 PMSA implementation
Figure G-2 shows the CP15 registers in an ARMv6 PMSA implementation:
ARMv6 Differences
CRn opc1 CRm opc2
c0 0 c0
0
MIDR, Main ID Register
1
CTR, Cache Type Register
2
TCMTR, TCM Type Register
4
MPUIR, MPU Type Register
{3,5-7} Aliases of Main ID Register
*{c1-c7} *{0-7} *CPUID Registers, optional
c1 0 c0
0
SCTLR, System Control Register
1
ACTLR, Auxiliary Control Register, IMPLEMENTATION DEFINED
2
CPACR, Coprocessor Access Control Register
c5 0 c0 {0,1}
Fault Status Registers
c6 0 c0
{0-2}
Fault Address Registers
c1 {0,1}
Memory Region Base Address registers
{2,3}
Memory Region Size and Enable registers
{4,5} Memory Region Access Control registers
c2 0 RGNR, MPU Region Number Register
c7 0
c0 4
CP15WFI, Wait for interrupt operation
c5
{0-2}
Cache maintenance operations
4
CP15ISB, Instruction barrier operation
{6,7}
Branch predictor maintenance operations
{c6,c7} {0-2}
Cache maintenance operations
c10
{0-3}
Cache maintenance operations
{4,5}
Data barrier operations
6
CDSR, Cache Dirty Status Register
c11 {0-2}
Cache maintenance operations
c12 {4,5} ‡ Block transfer operations, optional
c14 {0-3} ‡ Cache maintenance operations
c9 0 c0 {0,1}
Cache Lockdown (format C) operations
c1 {0,1}
TCM Region registers
c2
0
TCMSR, TCM Selection Register
{c5,c6} {0,1}
Cache Lockdown (format D) operations
c11 {0-7} {c0-c8,c15} {0-7} ‡ Reserved for DMA support for TCM operations
c13 0 c0 1
CONTEXTIDR, Context ID Register
c15 {0-7} {c0-c15} {0-7} ‡ IMPLEMENTATION DEFINED registers
Read-only
Read/Write
Write-only
Bold text = Accessible in User mode
*
Not available in all versions of ARMv6
‡ Access depends on operation
Figure G-2 CP15 registers in an ARMv6 PMSA implementation
ARM DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. AppxG-31