ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Instruction Details
A8.6.348 VPADAL
Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements of a vector, and accumulates the
absolute values of the results into the elements of the destination vector.
The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers.
The result elements are twice the length of the operand elements.
Figure A8-2 shows an example of the operation of VPADAL.
Encoding T1 / A1 Advanced SIMD
VPADAL. ,
VPADAL. ,
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 D 1 1 size 0 0 Vd 0 1 1 0 op Q M 0 Vm
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 D 1 1 size 0 0 Vd 0 1 1 0 op Q M 0 Vm
if size == ‘11’ then UNDEFINED;
if Q == ‘1’ && (Vd == ‘1’ || Vm == ‘1’) then UNDEFINED;
unsigned = (op == ‘1’);
esize = 8