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ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

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Debug Events<br />

2. The processor takes the SMC exception, branching to the Monitor vector in Monitor mode. The<br />

SCR.NS bit is set to 1, indicating the SMC originated in the Non-secure state.<br />

3. The Vector Catch debug event is taken. Although SCR.NS is set to 1, the processor is in the Secure<br />

state because it is in Monitor mode.<br />

4. The processor jumps to the Secure Prefetch Abort vector, <strong>and</strong> sets SCR.NS to 0.<br />

Note<br />

Aborts taken in Secure state cause SCR.NS to be set to 0.<br />

5. The abort h<strong>and</strong>ler at the Secure Prefetch Abort h<strong>and</strong>ler can tell a Vector Catch debug event occurred,<br />

<strong>and</strong> can determine the address of the SMC instruction from LR_mon. However, it cannot determine<br />

whether that is a Secure or Non-secure address.<br />

Therefore, <strong>ARM</strong> recommends that you do not program a Vector Catch debug event on the SMC vector when<br />

Monitor debug-mode is enabled.<br />

Note<br />

This is not a security issue, because the sequence given here can only occur if SPIDEN is HIGH.<br />

Possible effect of the Security Extensions on FIQ vector catch<br />

When the Security Extensions are implemented, a debugger might need to consider the implications of the<br />

SCR on a Vector Catch event set on the FIQ vector, when the SCR is configured with both:<br />

the SCR.FW bit set to 0, so the CPSR.F bit cannot be modified in Non-secure state<br />

the SCR.FIQ bit set to 0, so that FIQs are h<strong>and</strong>led in FIQ mode.<br />

With this configuration, if an FIQ occurs in Non-secure state, the processor does not set CPSR.F to disable<br />

FIQs, <strong>and</strong> so the processor repeatedly takes the FIQ exception.<br />

It might not be possible to debug this situation using the vector catch on FIQ because the instruction at the<br />

FIQ exception vector is never committed for execution <strong>and</strong> therefore the debug event never occurs.<br />

C3.2.7 Pseudocode details of Software debug events<br />

The following subsections give pseudocode details of Software debug events:<br />

Debug events<br />

Breakpoints <strong>and</strong> Vector Catches on page C3-28<br />

Watchpoints on page C3-35.<br />

Debug events<br />

The following functions cause the corresponding debug events to occur:<br />

BKPTInstrDebugEvent()<br />

<strong>ARM</strong> DDI 0406B Copyright © 1996-1998, 2000, 2004-2008 <strong>ARM</strong> Limited. All rights reserved. C3-27

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