ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition

Register Index
Register In a Description, see
Instruction Fault Address PMSA c6, Instruction Fault Address Register (IFAR) on page B4-58
VMSA c6, Instruction Fault Address Register (IFAR) on page B3-125
Instruction Fault Status PMSA c5, Instruction Fault Status Register (IFSR) on page B4-56
Instruction Memory Region
Cacheability, pre-ARMv6
Instruction Memory Region Extended
Access Permissions, pre-ARMv6
Instruction Memory Region,
pre-ARMv6
Instruction Memory Region Access
Permissions, pre-ARMv6
Instruction Region Access
Control
Instruction Region Base
Address
Instruction Region Size and
Enable
VMSA c5, Instruction Fault Status Register (IFSR) on page B3-122
c2, Memory Region Cacheability Registers (DCR and ICR) on
page AppxH-44
c5, Memory Region Extended Access Permissions Registers (DEAPR
and IEAPR) on page AppxH-46
c6, Memory Region registers (DMRR0-DMRR7 and IMRR0-IMRR7) on
page AppxH-47
c5, Memory Region Access Permissions Registers (DAPR and IAPR) on
page AppxH-45
PMSA c6, Instruction Region Access Control Register (IRACR) on page B4-65
PMSA c6, Instruction Region Base Address Register (IRBAR) on page B4-61
PMSA c6, Instruction Region Size and Enable Register (IRSR) on page B4-63
Instruction Set Attribute CP15 c0, Instruction Set Attribute registers on page B5-19
Instruction TCM Non-Secure Access
Control, ARMv6
c9, TCM Non-Secure Access Control Registers, DTCM-NSACR and
ITCM-NSACR on page AppxG-51
Instruction TCM Region, ARMv6 c9, TCM Region Registers (DTCMRR and ITCMRR) on page AppxG-47
Instruction TLB Lockdown Register,
pre-ARMv7
Table K-1 Register index (continued)
c10, VMSA TLB lockdown support on page AppxH-59
Instruction Transfer Register, Debug Instruction Transfer Register (DBGITR) on page C10-46
Integration Mode Control Integration Mode Control Register (DBGITCTRL) on page C10-91
Interrupt Enable Clear c9, Interrupt Enable Clear Register (PMINTENCLR) on page C10-119
Interrupt Enable Set c9, Interrupt Enable Set Register (PMINTENSET) on page C10-118
Interrupt Status VMSA c12, Interrupt Status Register (ISR) on page B3-150
AppxK-14 Copyright © 1996-1998, 2000, 2004-2008 ARM Limited. All rights reserved. ARM DDI 0406B